ISPGDXTMFAMILY LATTICE [Lattice Semiconductor], ISPGDXTMFAMILY Datasheet - Page 15

• Manufacturer Part Number: ISPGDXTMFAMILY
• Description: In-System Programmable Generic Digital CrosspointTM
• Manufacturer: LATTICE [Lattice Semiconductor]

The ispGDX devices are identified either by the 32-bit
JTAG IDCODE register or the eight-bit ISP register. The
device ID assignments are listed in Table 4.
The ispJTAG programming is accomplished by execut-
ing Lattice private instructions under the Boundary Scan
State Machine.
Lattice ISP programming is accomplished by driving
BSCAN/ispEN low, while following the ISP state machine
Figure 8. Boundary Scan State Machine
Table 4. ispGDX Device ID Codes
Boundary Scan / ISP Programming and Test Options (Continued)
ispGDX80A
ispGDX120A
ispGDX160/A
DEVICE
8-BIT ISP ID
0111 0111
0111 1000
0111 1001
0
1
TMS or
TDI
TCK
TDO
tsu = 0.1 s (min.)
Run-Test/Idle
Test-Logic-Reset
0
0000 0000 0010 0101 0001 0000 0100 0011
0000 0000 0010 0101 0010 0000 0100 0011
0000 0000 0010 0101 0011 0000 0100 0011
1
tsu
32-BIT BOUNDARY SCAN IDCODE
1
0
1
Select-DR-Scan
Capture-DR
Update-DR
Exit2-DR
Exit1-DR
Pause-DR
Shift-DR
th = 0.1 s (min.)
th
0
0
0
1
1
1
0
15
1
0
0
Specifications ispGDX Family
algorithm. The eight-bit device ID can be read from the
device in Idle State for ISP device identification. Details
of the programming sequence are transparent to the user
and are handled by Lattice ISP Daisy Chain Downlowad
(ispDCD), ispCODE ‘C’ routines or any third-party pro-
grammers. Contact Lattice Technical Support to obtain
more detailed programming information.
1
tco
0
tco = 0.1 s (min.)
1
Select-IR-Scan
1
Capture-IR
Pause-IR
Update-IR
Exit1-IR
Shift-IR
Exit2-IR
0
0
1
0
1
1
GDX ID Codes
0
1
0
0
1