MT88E43AE ZARLINK [Zarlink Semiconductor Inc], MT88E43AE Datasheet - Page 2

• Manufacturer Part Number: MT88E43AE
• Description: Extended Voltage Calling Number Identification Circuit 2
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

MT88E43
Pin Description
5-54
Pin #
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
TRIGRC Trigger RC (Open Drain Output/Schmitt Input). Used to set the (RC) time interval from
TRIGout Trigger Out (CMOS Output). Schmitt trigger buffer output. Used to indicate detection of line
OSCout Oscillator Output. A 3.579545MHz crystal should be connected between this pin and OSCin.
TRIGin Trigger Input. Schmitt trigger buffer input. Used for line reversal and ring detection.
PWDN Power Down (Schmitt Input). Active high. When high, the device consumes minimal power by
FSKen FSK Enable (CMOS Input). Must be high for FSK demodulation. This pin should be set low to
MODE 3-wire interface: Mode Select (CMOS Input). When low, selects interface mode 0. When high,
OSCin
Name
DCLK
DATA
CAP
V
IN+
V
GS
IN-
IC
Ref
SS
Non-inverting Input of the internal opamp.
Inverting Input of the internal opamp.
Gain Select (Output) of internal opamp. The opamp’s gain should be set according to the
nominal Vdd of the application using the information in Figure 10.
Reference Voltage (Output). Nominally V
Capacitor. A 0.1 F decoupling capacitor should be connected across this pin and V
TRIGin going low to TRIGout going high. An external resistor connected to V
connected to V
reversal and/or ringing.
selects interface mode 1. See pin 16 (DCLK) description to understand how MODE affects the
DCLK pin.
Oscillator Input. A 3.579545MHz crystal should be connected between this pin and OSCout. It
may also be driven directly from an external clock source.
When OSCin is driven by an external clock, this pin should be left open.
Power Supply Ground.
Internal Connection. Must be connected to V
disabling all functionality except TRIGin, TRIGRC and TRIGout. Must be pulled low for device
operation.
prevent the FSK demodulator from reacting to extraneous signals (such as speech, alert signal
and DTMF which are all in the same frequency band as FSK).
3-wire Interface: Data Clock (CMOS Input/Output). In mode 0 (MODE pin low), this pin is an
output. In mode 1 (MODE pin high), this pin is an input.
3-wire Interface: Data (CMOS Output). In mode 0 data appears at the pin once demodulated.
In mode 1 data is shifted out on the rising edge of the microcontroller supplied DCLK.
SS
determine the duration of the (RC) time interval.
TRIGRC
TRIGout
OSCout
TRIGin
MODE
OSCin
VRef
CAP
VSS
Figure 2 - Pin Connections
IN+
GS
IN-
10
11
12
1
2
3
4
5
6
7
8
9
Description
DD
24
23
22
21
20
19
18
17
16
15
14
13
/2
SS
. It is used to bias the input opamp.
for normal operation.
VDD
St/GT
ESt
StD
INT
CD
DR
DATA
DCLK
FSKen
PWDN
IC
DD
Data Sheet
and capacitor
SS
.