MT88L89AC MITEL [Mitel Networks Corporation], MT88L89AC Datasheet - Page 4

• Manufacturer Part Number: MT88L89AC
• Description: 3V Integrated DTMFTransceiver with Adaptive Micro Interface
• Manufacturer: MITEL [Mitel Networks Corporation]

MT88L89
Following the filter section is a decoder employing
digital
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals such as voice while
providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the “signal condition” in
some industry specifications) the “Early Steering”
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an inactive state.
Steering Circuit
Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred
to as character recognition condition). This check is
performed by an external RC time constant driven by
ESt. A logic high on ESt causes v
rise as the capacitor discharges. Provided that the
signal condition is maintained (ESt remains high) for
the validation period (t
4-128
F
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941
LOW
Table 1. Functional Encode/Decode Table
counting
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
0= LOGIC LOW, 1= LOGIC HIGH
F
HIGH
techniques
DIGIT
GTP
C
D
A
B
1
2
3
4
5
6
7
8
9
0
#
*
), v
c
D
reaches the threshold
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
3
to
c
(see Figure 5) to
D
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
determine
2
D
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
D
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
the
(V
latching 62its corresponding 4-bit code (see Table 1)
into the Receive Data Register. At this point the GT
output is activated and drives v
continues to drive high as long as ESt remains high.
Finally, after a short delay to allow the output latch to
settle, the delayed steering output flag goes high,
signalling that a received tone pair has been
registered. The status of the delayed steering flag
can be monitored by checking the appropriate bit in
the status register. If Interrupt mode has been
selected, the IRQ/CP pin will pull
delayed steering flag is active.
The contents of the output latch are updated on an
active delayed steering transition. This data is
presented to the four bit bidirectional data bus when
the Receive Data Register is read. The steering
circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting
signals too short to be considered valid, the receiver
will tolerate signal interruptions (drop out) too short
to be considered a valid pause. This facility, together
with the capability of selecting the steering time
constants externally, allows the designer to tailor
performance to meet a wide variety of system
requirements.
Guard Time Adjustment
The simple steering circuit shown in Figure 5 is
adequate for most applications. Component values
are chosen according to the following inequalities
(see Figure 7):
The value of t
Electrical Characteristics) and t
TSt
V
MT88L89
) of the steering logic to register the tone pair,
DD
St/GT
V
ESt
DD
Figure 5 - Basic Steering Circuit
t
t
REC
REC
t
t
DO
ID
DP
t
t
DAmax
t
t
DPmax
DAmin
DPmin
is a device parameter (see AC
t
t
GTP
GTA
R1
= (R1C1) In [V
+ t
= (R1C1) In (V
+ t
+ t
+ t
GTAmax
GTAmin
GTPmax
GTPmin
Vc
C1
REC
- t
- t
- t
- t
DD
DPmin
DD
DPmax
DAmax
DAmin
is the minimum
low when
c
/ (V
/ V
to V
TSt
DD
-V
)
TSt
DD
)]
. GT
the