HI-15530CDM HOLTIC [Holt Integrated Circuits], HI-15530CDM Datasheet - Page 4

• Manufacturer Part Number: HI-15530CDM
• Description: Manchester Encoder / Decoder
• Manufacturer: HOLTIC [Holt Integrated Circuits]

DECODER OPERATION
The Decoder requires a single clock with a frequency of 12
times the desired data rate applied at the DECODER
CLOCK input. The Manchester II coded data can be
presented to the Decoder in one of two ways. The
BIPOLAR ONE and BIPOLAR ZERO inputs will accept
data from a comparator sensed transformer coupled bus as
specified in MIL-STD-1553. The UNIPOLAR DATA input
can only accept non-inverted Manchester II coded data
(e.g. from
Decoder is free running and continuously monitors its data
input lines for a valid sync character and two valid
Manchester data bits to start an output cycle. When a valid
sync is recognized (1), the type of sync is indicated on
COMMAND/
a command sync, this output will go high (2) and remain
high for sixteen DECODER SHIFT CLOCK periods (3),
otherwise it will remain low. The TAKE DATA output will go
high and remain high (2) - (3) while the Decoder is
transmitting the decoded data through SERIAL DATA OUT.
The decoded data available at SERIAL DATA OUT is in a
NRZ format. The DECODER SHIFT CLOCK is provided so
that the decoded bits can be shifted into an external register
on every low-to-high transition of this clock (2) - (3). After all
sixteen decoded bits have been transmitted (3) the data is
checked for odd parity. A high on VALID WORD output (4)
indicates a successful reception of a word without any
Manchester or parity errors. At this time the Decoder is
VALID WORD
COMMAND /
DATA
TAKE DATA
SHIFT CLK
DECODER
DATA OUT
BIPOLAR
BIPLOAR
ZERO IN
SERIAL
TIMING
ONE IN
BIPOLAR ZERO OUT
SYNC
DATA
SYNC output. If the sync character was
May be high from previous reception
SYNC
SYNC
0
UNDEFINED
1
SYNC
SYNC
of an Encoder). The
2
HOLT INTEGRATED CIRCUITS
15
15
3
14
14
4
(1)(2)
13
13
5
15
12
12
4
HI-15530
6
14
looking for a new sync character to start another output
sequence. VALID WORD will go low approximately 20
DECODER SHIFT CLOCK periods after it goes high if not
reset low sooner by a valid sync and two valid Manchester
bits as shown (1). At any time in the above sequence, a
high input on DECODER RESET during a low-to-high
transition of DECODER SHIFT CLOCK will abort
transmission and initialize the Decoder to start looking for a
new sync character.
11
11
7
UNIPOLAR
DECODER
BIPOLAR
BIPOLAR
13
MASTER
ZERO IN
DATA IN
ONE IN
RESET
CLK
10
10
8
12
SYNCHRONIZER
16
2
2
TRANSITION
4
FINDER
17
1
1
3
DECODER
RESET
18
0
0
2
19
P
P
1
COUNTER
0
RATE
CLK
CHARACTER
BIT
IDENTIFIER
BIT
(3)
PARITY
CHECK
(4)
COMMAND/
TAKE DATA
SERIAL DATA
SHIFT CLK
DECODER
SYNC
WORD
VALID
OUT
DATA