24LC1025ESM Microchip Technology Inc., 24LC1025ESM Datasheet
24LC1025ESM
Manufacturer Part Number
24LC1025ESM
Description
SOP-8
Manufacturer
Microchip Technology Inc.
Datasheet
1.24LC1025ESM.pdf
(22 pages)
Specifications of 24LC1025ESM
Date_code
10+
Device Selection Table:
Features:
• Single supply with operation down to 1.7V for
• Low-power CMOS technology:
• 2-wire serial interface, I
• Cascadable up to four devices
• Schmitt Trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz and 400 kHz clock compatibility
• 1 MHz clock for FC versions
• Page write time 3 ms, typical
• Self-timed erase/write cycle
• 128-byte page write buffer
• Hardware write-protect
• ESD protection >400V
• More than 1 million erase/write cycles
• Data retention >200 years
• Factory programming available
• Packages include 8-lead PDIP, SOIJ
• Pb-free and RoHS compliant
• Temperature ranges:
Description:
The Microchip Technology Inc. 24AA1025/24LC1025/
24FC1025 (24XX1025*) is a 128K x 8 (1024K bit)
Serial Electrically Erasable PROM, capable of opera-
tion across a broad voltage range (1.8V to 5.5V). It has
been developed for advanced, low-power applications
such as personal communications or data acquisition.
This device has both byte write and page write
capability of up to 128 bytes of data.
© 2007 Microchip Technology Inc.
†
*100 kHz for V
24AA1025
24LC1025
24FC1025
100 kHz for V
24AAXX devices, 2.5V for 24LCXX devices
- Read current 1 mA, typical
- Standby current 100 nA, typical
- Industrial (I):
- Automotive (E):-40°C to +125°C
Number
Part
CC
CC
1.7-5.5V
2.5-5.5V
2.5-5.5V
Range
V
< 4.5V, E-temp.
< 2.5V.
CC
-40°C to +85°C
1024K I
2
C™ compatible
Max. Clock
Frequency
400 kHz
400 kHz*
1 MHz
24AA1025/24LC1025/24FC1025
†
2
C
™
Ranges
Temp
I, E
CMOS Serial EEPROM
I
I
Preliminary
*24XX1025 is used in this document as a generic part number
for the 24AA1025/24LC1025/24FC1025 devices.
This device is capable of both random and sequential
reads. Reads may be sequential within address bound-
aries 0000h to FFFFh and 10000h to 1FFFFh.
Functional address lines allow up to four devices on the
same data bus. This allows for up to 4 Mbits total
system EEPROM memory. This device is available in
the standard 8-pin PDIP and SOIJ packages.
Package Type
Block Diagram
SDA
I/O
PDIP
SOIJ
Control
Logic
V
V
I/O
CC
SS
SCL
V
A0
A1
A2
V
SS
A0
A1
A2
A0 A1
SS
Memory
Control
Logic
1
2
3
4
1
2
3
4
WP
XDEC
8
7
6
5
8
7
6
5
V
WP
SCL
SDA
DS21941E-page 1
V
WP
SCL
SDA
CC
CC
HV Generator
Page Latches
R/W Control
Sense AMP
EEPROM
Array
YDEC
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