LTC2272IUJ Linear Technology Corporation, LTC2272IUJ Datasheet

LTC2272IUJ

Manufacturer Part Number

LTC2272IUJ

Description

Manufacturer

Linear Technology Corporation

Datasheets

1.LTC2273IUJ.pdf (44 pages)

2.LTC2272IUJ.pdf (44 pages)

Specifications of LTC2272IUJ

Case

QFN

Date_code

08+

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

LTC2272IUJ#PBF/CUJ

Manufacturer:

Quantity:

969

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FEATURES

APPLICATIONS

2.2μF

TYPICAL APPLICATION

ANALOG

INPUT

High Speed Serial Interface (JESD204)

Sample Rate: 80Msps/65Msps

77.7dBFS Noise Floor

100dB SFDR

SFDR >90dB at 140MHz (1.5V

PGA Front End (2.25V

700MHz Full Power Bandwidth S/H

Optional Internal Dither

Single 3.3V Supply

Power Dissipation: 1100mW/990mW

Clock Duty Cycle Stabilizer

Pin Compatible Family

40-Pin 6mm × 6mm QFN Package

Telecommunications

Receivers

Cellular Base Stations

Spectrum Analysis

Imaging Systems

ATE

–

105Msps: LTC2274

80Msps: LTC2273

65Msps: LTC2272

COMMON MODE

–

ENC

CLOCK/DUTY

BIAS VOLTAGE

CONTROL

AMP

S/H

CYCLE

1.25V

ENC

CLOCK

–

PGA

INTERNAL ADC

GENERATOR

DITH

REFERENCE

PIPELINED

ADC CORE

16-BIT

3.3V

MSBINV

SENSE

P-P

SHDN

or 1.5V

CORRECTION

LOGIC

P-P

PAT1 PAT0

P-P

SCRAMBLER/

GENERATOR

Input Range)

ENCODER

PATTERN

8B/10B

FAM

Input Range)

SCRAM

SRR1 SRR0

SERIALIZER

PLL

20X

GND

SYNC

CMLOUT

DESCRIPTION

The LTC

converters with a high speed serial interface. They are

designed for digitizing high frequency, wide dynamic

range signals with an input bandwidth of 700MHz. The

input range of the ADC can be optimized using the PGA

front end. The output data is serialized according to the

JEDEC serial interface for data converters speciﬁ cation

(JESD204).

The LTC2273/LTC2272 are perfect for demanding applica-

tions where it is desirable to isolate the sensitive analog

circuits from the noisy digital logic. The AC performance

includes a 77.7dB Noise Floor and 100dB spurious free

dynamic range (SFDR). Ultra low internal jitter of 80fs

RMS allows undersampling of high input frequencies

with excellent noise performance. Maximum DC specs

include ±4.5LSB INL and ±1LSB DNL (no missing codes)

over temperature.

The encode clock inputs, ENC

differentially or single-ended with a sine wave, PECL,

LVDS, TTL or CMOS inputs. A clock duty cycle stabilizer

allows high performance at full speed with a wide range

of clock duty cycles.

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other

trademarks are the property of their respective owners.

0.1μF

–

1.2V TO 3.3V

0.1μF

–

3.3V

0.1μF

2273/LTC2272 are 80Msps/65Msps, 16-bit A/D

16-Bit, 80Msps/65Msps

50Ω

ASIC OR FPGA

50Ω

–

RECEIVER

SERIAL

Serial Output ADC

LTC2273/LTC2272

22732 TA01

–100

–110

–120

–130

–10

–20

–30

–40

–50

–60

–70

–80

–90

128k Point FFT, f

and ENC

–1dBFS, PGA = 0

FREQUENCY (MHz)

–

, may be driven

= 4.93MHz,

22732f

22732 G04

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