Cypress Semiconductor Corporation., Datasheet

Manufacturer Part Number

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY7C64713128AXC.pdf (50 pages)

Specifications of

Case

QFP

Date_code

07+

Current page: 1 of 50
Download datasheet (759Kb)

Cypress Semiconductor Corporation

Document #: 38-08039 Rev. *B

1.0

• Single-chip integrated USB transceiver, SIE, and

• Fit, form and function upgradable to the FX2LP

• Draws no more than 65 mA in any mode making the FX1

• Software: 8051 runs from internal RAM, which is:

• 16 KBytes of on-chip Code/Data RAM

• Four programmable BULK/INTERRUPT/ISOCH-

• Additional programmable (BULK/INTERRUPT) 64-byte

• 8- or 16-bit external data interface

• Smart Media Standard ECC generation

• GPIF

enhanced 8051 microprocessor

(CY7C68013A)

suitable for bus powered applications

RONOUS endpoints

endpoint

— Pin-compatible

— Object-code-compatible

— Functionally-compatible (FX1 functionality is a

— Downloaded via USB

— Loaded from EEPROM

— External memory device (128-pin configuration only)

— Buffering options: double, triple, and quad

— Allows direct connection to most parallel interfaces;

— Programmable waveform descriptors and configu-

Subset of the FX2LP)

8- and 16-bit

ration registers to define waveforms

Integrated

full-speed XCVR

Features

D+

D–

FX1

VCC

1.5k

connected for

enumeration

Enhanced USB core

Simplifies 8051 code

XCVR

USB

24 MHz

Ext. XTAL

x20

PLL

/0.5

/1.0

/2.0

Smart

Engine

USB

•

High-performance micro

with lower-power options

using standard tools

3901 North First Street

four clocks/cycle

Figure 1-1. Block Diagram

Easy firmware changes

12/24/48 MHz,

8051 Core

“Soft Configuration”

Full-speed USB Peripheral Controller

EZ-USB FX1™ USB Microcontroller

16 KB

RAM

• Integrated, industry standard 8051 with enhanced

• 3.3V operation with 5V tolerant inputs

• Smart SIE

• Vectored USB interrupts

• Separate data buffers for the Setup and DATA portions

• Integrated I

• 48-MHz, 24-MHz, or 12-MHz 8051 operation

• Four integrated FIFOs

• Vectored for FIFO and GPIF interrupts

• Up to 40 general purpose I/Os

• Three package options—128-pin TQFP, 100-pin TQFP,

features

of a CONTROL transfer

and 56-pin QFN Lead-free

— Supports multiple Ready (RDY) inputs and Control

— Up to 48-MHz clock rate

— Four clocks per instruction cycle

— Two USARTS

— Three counter/timers

— Expanded interrupt system

— Two data pointers

— Brings glue and FIFOs inside for lower system cost

— Automatic conversion to and from 16-bit buses

— Master or slave operation

— FIFOs can use externally supplied clock or

— Easy interface to ASIC and DSP ICs

(CTL) outputs

asynchronous strobes

ECC

•

FIFO and endpoint memory

(master or slave operation)

Additional I/Os (24)

C controller, runs at 100 or 400 KHz

San Jose

GPIF

FIFO

4 kB

Master

ADDR (9)

RDY (6)

CTL (6)

CA 95134

8/16

Revised February 14, 2005

CY7C64713/14

including two USARTS

standards such as

Up to 96 MBytes/s

programmable I/F

ATAPI, EPP, etc.

to ASIC/DSP or bus

Abundant I/O

General

burst rate

•

408-943-2600

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