ATR0622-EK1 ATMEL [ATMEL Corporation], ATR0622-EK1 Datasheet
ATR0622-EK1
Related parts for ATR0622-EK1
ATR0622-EK1 Summary of contents
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Features • 16 Channel GPS Correlator – 8192 Search Bins with GPS Acquisition Accelerator – Accuracy: 2.5m CEP (Stand-Alone, S/A off) – Time to First Fix: 34s (Cold Start) – Acquisition Sensitivity: –140 dBm – Tracking Sensitivity: –150 dBm ® ...
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Description The GPS baseband processor ATR0621P includes a 16-channel GPS correlator and is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture and very low power consump- tion. In addition, a large number of ...
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Figure 1-1. Block Diagram NSHDN NSLEEP XT_IN XT_OUT RF_ON CLK23 P15/ANTON P0/NANTSHORT P14/NAADET1 P25/NAADET0 P20/TIMEPULSE P29/GPSMODE12 P27/GPSMODE11 P26/GPSMODE10 P24/GPSMODE8 P23/GPSMODE7 P19/GPSMODE6 P17/GPSMODE5 P13/GPSMODE3 P12/GPSMODE2 P1/GPSMODE0 P9/EXTINT0 P2/BOOT_MODE P30/AGCOUT0 P8/STATUSLED P16/NEEPROM P11/EM_A21 P28/EM_A20 P10/EM_A0/NLB P7/NUB/NWR1 P6/NOE/NRD P5/NWE/NWR0 P4/nCS0 P3/nCS1 EM_A19 EM_A1 ...
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Architectural Overview 2.1 Description The ATR0621P architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It inter- faces the processor with the on-chip 32-bit ...
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Pin Configuration 3.1 Pinout Figure 3-1. Pinout LFBGA100 (Top View) Table 3-1. ATR0621P Pinout Pin Name LFBGA100 Pin Type CLK23 G9 IN DBG_EN H4 IN EM_A1 A6 OUT EM_A2 A5 OUT EM_A3 A4 OUT EM_A4 A2 OUT EM_A5 A3 ...
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Table 3-1. ATR0621P Pinout (Continued) Pin Name LFBGA100 Pin Type EM_A16 C6 OUT EM_A17 F8 OUT EM_A18 B3 OUT EM_A19 C5 OUT EM_DA0 B6 I/O EM_DA1 B10 I/O EM_DA2 C7 I/O EM_DA3 C10 I/O EM_DA4 D10 I/O EM_DA5 E7 I/O ...
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Table 3-1. ATR0621P Pinout (Continued) Pin Name LFBGA100 Pin Type I/O P10 E4 I/O P11 H10 I/O ...
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Table 3-1. ATR0621P Pinout (Continued) Pin Name LFBGA100 Pin Type TDI J2 IN TDO K3 OUT TMS J1 IN USB_DM F10 I/O USB_DP D3 I/O VBAT J7 IN (2) VBAT18 G6 OUT VDD18 E6 IN VDD18 F7 IN VDD18 F6 ...
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Signal Description Table 3-2. ATR0621P Signal Description Module Name Function EM_A0 to EM_A21 External memory address bus EM_DA0 to EM_DA15 External memory data bus NCS0 to NCS1 Chip select NCS2 to NCS3 Chip select NWR0 Lower byte write signal ...
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Table 3-2. ATR0621P Signal Description (Continued) Module Name Function SIGHI0 Digital IF SIGLO0 Digital IF GPS SIGHI1 Digital IF SIGLO1 Digital IF TIMEPULSE GPS synchronized time pulse GPSMODE0-12 GPS mode STATUSLED Status LED NEEPROM Enable EEPROM support CONFIG ANTON Active ...
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Setting GPSMODE0 to GPSMODE12 The start-up configuration of a ROM-based system without external non-volatile memory is defined by the status of the GPSMODE pins after system reset. Alternatively, the system can be configured through message commands passed through the ...
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Sensitivity Settings Table 3-5. GPSMODE3 (Fixed PU Notes: For all GPS receivers the sensitivity depends on the integration time of the GPS signals. There- fore there is a trade-off between sensitivity and the time to ...
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Both USART ports and the USB port accept input messages in all three supported protocols (NMEA, RTCM and UBX) at the configured baud rate. Input messages of all three protocols can be arbitrarily mixed. Response to a query input message ...
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The following settings apply if GPSMODE configuration is not enabled, that is, GPSMODE = 0 (ROM-Defaults): Table 3-11. Baud rate (kBaud) Input protocol Output protocol Messages Information messages (UBX INF or NMEA TXT) 3.3.4 USB Power Mode For correct response ...
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Table 3-13. Pin P0/NANTSHORT P25/NAADET0/ MISO or P14/NAADET1 P15/ANTON Table 3-14. GPSMODE11 (Reset = PU Note: The Antenna Supervisor Software will be configured as follows: 1. Enable Control Signal 2. Enable Short ...
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External Connections for a Working GPS System Figure 3-2. Example of an External Connection ATR0601 SIGH SIGL SC PuRF PuXTO +3V (see Power Supply) (see Power Supply) GND NC: Not connected ATR0621P 16 SIGHI SIGLO CLK23 RF_ON NSLEEP NC ...
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Table 3-15. Recommended Pin Connection Pin Name Recommended External Circuit P0/NANTSHORT Internal pull-down resistor, leave open if Antenna Supervision functionality is unused. Internal pull-down resistor, leave open, in order to disable the GPSMODE pin configuration feature. Connect to VDD18 to ...
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Table 3-15. Recommended Pin Connection (Continued) Pin Name Recommended External Circuit Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by P24/GPSMODE8/MOSI user application. Refer to GPSMODE definitions in section page ...
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Connecting an Optional FLASH Memory The ATR0621P offers the possibility to connect an external FLASH memory. The high perfor- mance ARM7 code, that is stored in the FLASH memory. The 32-bit RISC processor of the ATR0621 accesses the external ...
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Connecting an Optional Serial EEPROM The ATR0621P offers the possibility to connect an external serial EEPROM. The internal ROM firmware supports to store the configuration of the ATR0621P in serial EEPROM. The pin P16/NEEPROM signals the firmware that a ...
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Power Supply The baseband IC is supplied with four distinct supply voltages: • VDD18, the nominal 1.8V supply voltage for the core, the RF-I/O pins, the memory interface and the test pins and all GPIO-pins not mentioned in next ...
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The baseband IC contains a built in low dropout voltage regulator LDO18. This regulator can be used if the host system does not provide the core voltage VDD18 of 1.8V nominal. In such case, LDO18 will provide a 1.8V supply ...
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The USB Transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and USB_DP are connected to GND (internal pull-down resistors). The USB Transceiver is enabled if VDD_USB within 3.0V and 3.6V. Figure 4-3. External Wiring Example ...
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RTC Oscillator Figure 5-1. Crystal Connection 32.768 kHz 50 ppm can be derived from the crystal datasheet. Maximum value for pF. load load 6. Absolute Maximum Ratings Stresses ...
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Electrical Characteristics - DC Characteristics If no additional information is given in column Test Conditions, the values apply to a temperature range from –40°C to +85°C. No. Parameters Test Conditions 1.1 DC supply voltage core DC supply voltage VDDIO ...
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Electrical Characteristics - DC Characteristics (Continued additional information is given in column Test Conditions, the values apply to a temperature range from –40°C to +85°C. No. Parameters Test Conditions Low-level output voltage I OL 1.22 VDDIO domain ...
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Electrical Characteristics - DC Characteristics (Continued additional information is given in column Test Conditions, the values apply to a temperature range from –40°C to +85°C. No. Parameters Test Conditions Configurable input pull-up 1.37 resistor (idle state) Configurable ...
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LDO18 The LDO18 is a built in low dropout voltage regulator which can be used if the host system does not provide the core voltage VDD18. Table 11-1. Parameter Supply voltage LDO_IN Output voltage (LDO_OUT) Output current (LDO_OUT) Current ...
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... Ordering Information Extended Type Number Package ATR0621P-7FQY LFBGA100 ATR0621P-7FHW LFBGA100 ATR0622-EK1 ATR0622-DK1 14. Package LFBGA100 Package: R-LFBGA 100_G Dimensions Corner Top View technical drawings according to DIN specifications Drawing-No.: 6.580-5003.01-4 Issue: 2; 27.10.05 Moisture sensitivity level (MSL 4890H– ...
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Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4890H-GPS-08/08 4890G-GPS-01/08 4890F-GPS-09/07 4890E-GPS-06/07 4890D-GPS-12/06 4890C-GPS-10/06 4890B-GPS-06/06 ATR0621P 30 History Section 8 “Electrical ...
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Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to ...