ATR0635-7KQY ATMEL [ATMEL Corporation], ATR0635-7KQY Datasheet
ATR0635-7KQY
Related parts for ATR0635-7KQY
ATR0635-7KQY Summary of contents
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... Supports NMEA , UBX Binary and RTCM Protocol for DGPS • Supports SBAS (WAAS, EGNOS, MSAS) • Update Rate • Supports A-GPS (Aiding) • Excellent Noise Performance ® Processor Core ® ANTARIS4 Single-chip GPS Receiver SuperSense ATR0635 4928H–GPS–06/08 ...
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... Due to the fully integrated design, just an RF SAW filter, a GPS TCXO and blocking capacitors are required to realize a stand-alone GPS functionality. The ATR0635 includes a complete GPS firmware, licensed from u-blox AG, which performs the GPS operation, including tracking, acquisition, navigation and position data output. For normal PVT (Position/Velocity/Time) applications, there is no need for external Flash- or ROM-memory ...
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... Architectural Overview 2.1 Block Diagram Figure 2-1. ATR0635 Block Diagram PUXTO PURF VDD18 VDDIO VDD_USB VDIG VCC1 VCC2 VBP TEST MO RF NRF XTO NXTO X NX RF_ON NSHDN NSLEEP XT_IN XT_OUT P20/TIMEPULSE P29/GPSMODE12 P27/GPSMODE11 P26/GPSMODE10 P24/GPSMODE8 P23/GPSMODE7 P19/GPSMODE6 P17/GPSMODE5 P13/GPSMODE3 P12/GPSMODE2 P1/GPSMODE0 P14/NAADET1 P25/NAADET0 ...
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... General Description The ATR0635 has been designed especially for mobile applications. It provides high isolation between GPS and cellular bands, as well as very low power consumption. ATR0635 is based on the successful ANTARIS4 technology which includes the ANTARIS high performance SuperSense software in ROM, developed by u-blox AG, Switzerland. ANTARIS ...
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... The ARM standard In-Circuit Emulation debug interface is supported via the JTAG/ICE port of the ATR0635. The ATR0635 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It inter- faces the processor with the on-chip 32-bit memories and the external memories and devices by means of the External Bus Interface (EBI) ...
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... Pin Configuration 3.1 Pinout Figure 3-1. Pinning BGA96 (Top View Table 3-1. ATR0635 Pinout Pin Name BGA 96 Pin Type AGCO A4 Analog I/O CLK23 A8 Digital OUT DBG_EN E8 Digital IN EGC D4 Digital IN GDIG C5 Supply GND A6 Supply GND A9 Supply GND B11 Supply GND F5 Supply GND ...
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... Table 3-1. ATR0635 Pinout (Continued) Pin Name BGA 96 Pin Type GNDA B4 Supply GNDA D2 Supply GNDA E1 Supply GNDA E2 Supply GNDA E3 Supply GNDA F1 Supply GNDA F2 Supply GNDA F3 Supply GNDA G1 Supply GNDA H1 Supply LDOBAT_IN D11 Supply LDO_EN C11 Digital IN LDO_IN E11 Supply LDO_OUT E12 Supply ...
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... Table 3-1. ATR0635 Pinout (Continued) Pin Name BGA 96 Pin Type P20 G7 Digital I/O P21 E6 Digital I/O P22 D10 Digital I/O P23 F8 Digital I/O P24 H7 Digital I/O P25 G5 Digital I/O P26 B6 Digital I/O P27 F7 Digital I/O P28 E7 Digital I/O P29 D5 Digital I/O P30 G12 Digital I/O P31 C10 Digital I/O PURF G4 Digital IN PURF H4 Digital IN PUXTO ...
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... Table 3-1. ATR0635 Pinout (Continued) Pin Name BGA 96 Pin Type (3) VDD_USB A10 Supply VDD18 H9 Supply VDD18 G11 Supply VDD18 F12 Supply VDD18 B9 Supply VDD18 E5 Supply (4) VDDIO B5 Supply VDDIO H5 Supply VDIG A5 Supply X A2 Analog OUT XT_IN A12 Analog IN XT_OUT B12 Analog OUT XTO ...
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... GPSMODE0-12 DIGITAL IN F[6-8], H[6,7] G8 NEEPROM DIGITAL IN GPS D7 STATUSLED DIGITAL OUT G7 TIMEPULSE DIGITAL OUT ATR0635 10 Type Active Level Pin Description/Comment - Leave open, internal pull down Low Reset input; open drain with internal pull-up resistor Low Shutdown output, connect to LDO_EN (C11) - Enable LDO18 Low ...
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... Digital IF (sample clock) - Analog supply 3V - Analog supply 3V - Analog supply 3V - Analog Ground - Digital supply (radio) 1.8V - Core voltage 1.8V USB transceiver supply voltage (3.0V to 3.6V (USB enabled 2.0V (USB disabled)) - Variable I/O voltage 1.65V to 3.6V - Digital ground (radio) - Digital ground - 2.3V to 3.6V - 1.8V LDO18 output, max 2.3V to 3.6V - 1.5V to 3.6V - 1.8V LDOBAT Output ATR0635 11 ...
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... GPSMODE pins after system reset. Alternatively, the system can be configured through message commands passed through the serial interface after start-up. This configuration of the ATR0635 can be stored in an external non-volatile memory like EEPROM. Default designates settings used by ROM firmware if GPSMODE configuration is disabled (GPSMODE0 = 0) ...
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... Serial I/O Configuration The ATR0635 features a two-stage I/O-message and protocol-selection procedure for the two available serial ports. At the first stage, a certain protocol can be enabled or disabled for a given USART port or the USB port. Selectable protocols are RTCM, NMEA and UBX. At the second stage, messages can be enabled or disabled for each enabled protocol on each port ...
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... NMEA Port UBX Port Table 3-8. NMEA Port UBX Port Table 3-9. NMEA Port UBX Port Table 3-10. NMEA Port UBX Port ATR0635 14 Supported Messages at Setting Low Standard GGA, RMC NAV SOL, SVINFO MON EXCEPT Supported Messages at Setting Medium Standard GGA, RMC, GSA, GSV, GLL, VTG, ZDA ...
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... GGA, RMC, GSA, GSV User Notice, Warning, Error USB Power Modes 0 USB device is bus-powered (maximum current limit 100 mA) (1) 1 USB device is self-powered (default ROM value) 1. Leave open 16). ATR0635 USART1 USART2 NMEA UBX 57.6 57.6 UBX, NMEA, RTCM UBX, NMEA, RTCM NMEA UBX NAV: SOL, SVINFO ...
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... NANTSHORT) 3. Enable Open Circuit Detection via NAADET The antenna supervisor function may not be disabled by GPSMODE pin selection. If the antenna supervisor function is not used, please leave open ANTON, NANTSHORT and NAADET. ATR0635 16 Pin Usage of Active Antenna Supervisor Usage Meaning Active antenna short circuit detection ...
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... External Connections for a Working GPS System Figure 3-2. Example of an External Connection (ATR0635) LNA (optional) SAW ATR0610 GND +3V (see Power Supply) (see Power Supply) GND NC: Not connected 4928H–GPS–06/08 NC SIGHI NC SIGLO NC CLK23 RF NRF RF_ON PURF NSLEEP PUXTO NC NRESET NC TMS NC TCK NC TDI ...
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... Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE P29/GPSMODE12/NPCS3 definitions in P30/AGCOUT0 Internal pull-down resistor; leave open. P31/RXD1 Internal pull-up resistor; leave open if serial interface is not used. ATR0635 18 12. “Setting GPSMODE0 to GPSMODE12” on page “Setting GPSMODE0 to GPSMODE12” on page “Setting GPSMODE0 to GPSMODE12” on page “Setting GPSMODE0 to GPSMODE12” on page “ ...
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... Connecting an Optional Serial EEPROM The ATR0635 offers the possibility of connecting an external serial EEPROM. The internal ROM firmware supports storing the configuration of the ATR0635 in serial EEPROM. The pin P16/NEEPROM signals the firmware that a serial EEPROM is connected to the ATR0635. The ATR0635’s 32-bit RISC processor accesses the external memory via SPI (serial peripheral inter- face). For best results, use a 32-Kbit 1.8V serial EEPROM such as Atmel’ ...
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... Power Supply The ATR0635 is supplied with six distinct supply voltages: • The power supplies for the RF part (VCC1, VCC2, VBP) within 2.7V to 3.3V. • VDIG, the 1.8V supply of the digital pins of the RF part (SIGHI, SIGLO and CLK23). VDIG should be connected to VDD18. • VDD18, the nominal 1.8V supply voltage for the core, the I/O pins, the memory interface and the test pins and all GPIO pins not mentioned in next item. • ...
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... NSHDN 1. 3.6V The ATR0635 contains a built in low dropout voltage regulator LDO18. This regulator can be used if the host system does not provide the core voltage VDD18 of 1.8V nominal. In such case, LDO18 will provide a 1.8V supply voltage from any input voltage VDD between 2.3V and 3.6V. ...
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... The RTC section will be initialized properly if VDD18 is supplied first to the ATR0635. If VBAT is applied first, the current consumption of the RTC and backup SRAM is undetermined. Figure 4-2. Connecting Example: Common Power Supplies for RF and Digital Part Using the Internal LDOs 2.7V to 3.3V NSHDN 1 µF (X7R) 1. 3.6V The USB Transceiver is disabled if VDD_USB < ...
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... VCC1 VCC2 VBP VDIG LDO_IN LDO_EN LDO_OUT VDD18 VDDIO 1 µF (X7R) LDOBAT_IN VBAT VBAT18 1 µF (X7R) VDDUSB ATR0635 ATR0635 internal RF LDO18 ldoin ldoen ldoout Core 1.8V to 3.3V variable I/O domain LDOBAT ldobat_in vbat vbat18 VDD RTC backup memory USB SM and transceiver 23 ...
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... VCC1 VCC2 VBP VDIG LDO_IN NSHDN LDO_EN LDO_OUT VDD18 1 µF (X7R) VDDIO LDOBAT_IN 1.5V to 3.6V VBAT VBAT18 1 µF (X7R) VDDUSB ATR0635 internal RF LDO18 ldoin ldoen ldoout Core 1.8V to 3.3V variable I/O domain LDOBAT ldobat_in vbat vbat18 VDD RTC backup memory USB SM and transceiver 4928H–GPS–06/08 ...
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... Crystals The ATR0635 requires a GPS TCXO. The reference frequency is 23.104 MHz. By connecting an optional RTC crystal, different power modes are available. The reference frequency is 32.768 kHz. 5.1 GPS Figure 5-1. Figure 5-2. 4928H–GPS–06/08 Equivalent Application Examples Using a GPS TCXO (See TCXO 4 ...
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... Figure 5-2 on page 25 Comment Sine wave or clipped sine wave Voltage peak-to-peak XT_IN 32 kHz Crystal Oscillator 32.768 kHz clock XT_OUT Min Typ Max Units 23.104 MHz 0.5 ±ppm 8 ±ppm –40.0 +85.0 °C 0.8 1 Min Typ Max Units 23.104 MHz 0.6 0.9 1.2 V ATR0635 internal RTC 4928H–GPS–06/08 ...
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... P14, P16 to P27, P29, P31 Note: Minimum/maximum limits are at +25°C ambient temperature, unless otherwise specified. 7. Handling The ATR0635 is an ESD-sensitive device. The current ESD values are to be defined. Observe proper precautions for handling. 8. Thermal Resistance Parameters Junction ambient according to JEDEC51-5 4928H– ...
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... SRAM, P9, P13, P22, P31, NSLEEP and NSHDN. The LDOBAT voltage regulator switches in battery mode if LDOBAT_IN falls below 1.5V. 3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT current is caused by outputs (pad output current as well as current across internal pull-up resistors) ATR0635 28 Pins Symbol ...
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... V 1.3 PU,on V 0.5 PU,off 1.65 1.8 1. 1.65 1 VDD18 O, VDDIO O,IO 0.3 V –0.3 IL,18 VDD18 0.7 VDD18 V IH,18 VDD18 + 0.3 0.7 V th+,CLK23 VDD18 0.3 V th-,CLK23 VDD18 ATR0635 Unit Type* kHz D kHz µA A µ µA A µ ...
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... SRAM, P9, P13, P22, P31, NSLEEP and NSHDN. The LDOBAT voltage regulator switches in battery mode if LDOBAT_IN falls below 1.5V. 3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT current is caused by outputs (pad output current as well as current across internal pull-up resistors) ATR0635 30 Pin CLK23 ...
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... C9 C9 C9, D9 Symbol Min Typ Max R 0.7 1 100 235 100 235 160 CPU R 40 160 CPD R 0.9 1.575 CPU R 1.425 3.09 CPU R 10 500 PD ATR0635 Unit Type ...
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... Power Consumption Table 11-1. Mode Sleep Shutdown Normal *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATR0635 32 Power Consumption Conditions At 1.8V, no CLK23 RTC, backup SRAM and LDOBAT Satellite acquisition Normal tracking on 6 channels with 1 fix/s; each additional active tracking channel adds 0.5 mA All channels disabled Typ ...
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... Ordering Information Extended Type Number ATR0635-7KQY ATR0635-EK1 ATR0635-DK1 13. Package Information Package: BGA96 Dimensions Corner Top View Pin A1 Laser Marking technical drawings according to DIN specifications Drawing-No.: 6.580-5005.01-4 Issue: 2; 31.05.06 Note: 1. All dimensions and tolerance conform to ASME Y 14.5M-1994 Dimension is measured at the maximum solder ball diameter, parallel to primary datum C 2 ...
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... Section 10 “Electrical Characteristics” numbers 2.6 and 2.7 on page 29 deleted Section 10 “Electrical Characteristics” numbers 4.2, 6.7 and 6.26 to 6.35 on pages changed Table 3-1 “ATR0635 Pinout” on page 6 changed Section 9 “Electrical Characteristics” numbers 6.31 and 6.32 on page 31 changed Table 3-2 “Signal Description” on pages changed Table 10-1 “Power Consumption” on page 32 changed Put datasheet in a new template Table 3-11 “ ...
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