HFDOM40MVXXX HANBIT [Hanbit Electronics Co.,Ltd], HFDOM40MVXXX Datasheet - Page 11

• Manufacturer Part Number: HFDOM40MVXXX
• Description: 40Pin Disk On Module Min.16MB ~ Max.768MB, True IDE Interface Mode, 3.3V / 5.0V Operating
• Manufacturer: HANBIT [Hanbit Electronics Co.,Ltd]

HANBit
Card Address Register
This register is provided for compatibility with the AT disk drive interface. It is recommended that this
register not be mapped into the host’s I/O space because of potential conflicts on Bit 7. The bits are defined
as follows:
Bit 7: This bit is reserved.
Implementation Note:
Conflicts may occur on the host data bus when this bit is provided by a Floppy Disk Controller
operating at the same addresses as the CompactFlash Storage Card. Following are some possible
solutions to this problem for the PCMCIA implementation:
1) Locate the CompactFlash Storage Card at a non-conflicting address, i.e. Secondary address (377)
or in an independently decoded Address Space when a Floppy Disk Controller is located at the
Primary addresses.
2) Do not install a Floppy and a CompactFlash Storage Card in the system at the same time.
3) Implement a socket adapter which can be programmed to (conditionally) tri-state D7 of I/0 address
3F7h/377h when a CompactFlash Storage Card is installed and conversely to tri-state
D6-D0 of I/O addresses 3F7h/377h when a floppy controller is installed.
4) Do not use the CompactFlash Storage Card’s Drive Address register. This may be accomplished
by either a) If possible, program the host adapter to enable only I/O addresses 1F0h-1F7h, 3F6h (or
170h-177h, 176h) to the CompactFlash Storage Card or b) if provided use an additional Primary /
Secondary configuration in the CompactFlash Storage Card which does not respond to accesses to
I/O locations 3F7h and 377h. With either of these implementations, the host software must not
attempt to use information in the Drive Address Register.
Bit 6 (-WTG): This bit is 0 when a write operation is in progress, otherwise, it is 1.
Bit 5 (-HS3): This bit is the negation of bit 3 in the Drive/Head register.
Bit 4 (-HS2): This bit is the negation of bit 2 in the Drive/Head register.
Bit 3 (-HS1): This bit is the negation of bit 1 in the Drive/Head register.
Bit 2 (-HS0): This bit is the negation of bit 0 in the Drive/Head register.
Bit 1 (-nDS1): This bit is 0 when drive 1 is active and selected.
Bit 0 (-nDS0): This bit is 0 when the drive 0 is active and selected.
Data Register
The Data Register is a 16-bit register, and it is used to transfer data blocks between the CompactFlash
Storage Card data buffer and the Host. This register overlaps the Error Register. The table below describes
the combinations of data register access and is provided to assist in understanding the overlapped Data
Register and Error/Feature Register rather than to attempt to define general PCMCIA word and byte
access modes and operations. See the PCMCIA PC Card Standard Release 2.0 for definitions of the Card
Accessing Modes for I/O and Memory cycles.
Feature Register
This register provides information regarding features of the CompactFlash Storage Card that the
host can utilize. This register is also accessed on data bits D15-D8 during a write operation to
Offset 0 with -CE2 low and -CE1 high.
URL:www.hbe.co.kr
Rev. 1.0 (January. 2004)
15
7
7
D7
X
14
6
6
-WTG
D6
13
5
5
-HS3
D5
Command specific
12
4
4
Data (15:8)
Data (7:0)
-HS2
11
D4
3
3
10
2
2
11 / 11
-HS1
D3
9
1
1
-HS0
D2
8
0
0
-nDS1
HFDOM40MVxxx
D1
HANBit Electronics Co., Ltd.
-nDS0
D0