HFDOM44P-016S1 HANBIT [Hanbit Electronics Co.,Ltd], HFDOM44P-016S1 Datasheet - Page 6

• Manufacturer Part Number: HFDOM44P-016S1
• Description: 44Pin Flash Disk Module Min.16MB~Max.512MB, True IDE Interface Mode, 3.3V/5.0V Operating
• Manufacturer: HANBIT [Hanbit Electronics Co.,Ltd]

HANBit
Signal Descriptions
URL : www.hbe.co.kr
REV 1.0 (August.2002)
A[2:0]
-PDIAG
-DASP(LED)
-CS0, -CS1
D[15:00]
GND
-IOR
-IOW
IRQ
-RESET
VCC
IORDY
-IOIS16
Table 2.2 Signal Descriptions
Signal Name
Dir.
I/O
I/O
I/O
--
O
--
O
O
I
I
I
I
I
11,12,13,
14,15,16,
33,35,36
7,8,9,10,
2,19,22,
3,4,5,6,
24,26,
30,40,
37,38
17,18
41,42
Pin
34
39
43
25
23
31
27
32
1
In True IDE Mode only A[2:0] are used to select the one of eight registers in
the Task File, the remaining address lines should be grounded by the host.
This input / output is the Pass Diagnostic signal in the Master / Slave
handshake protocol.
This signal used either to drive an LED whenever the Disk Module is being
accessed or as indication of a second drive present. This signal is active low
when the Disk Module is busy.
CS0 is the chip select for the task file registers while CS2 is used to select
the Alternate Status Register and the Device Control Register.
All Task File operations occur in byte mode on the low order bus D00-D07
while all data transfers are 16 bit using D00-D15.
Ground.
This is an I/O Read strobe generated by the host.
The I/O Write strobe pulse is used to clock I/O data on the Card Data bus
into the Storage Card controller registers when the Storage Card is
configured to use the I/O interface. The clocking will occur on the negative to
positive edge of the signal (trailing edge).
This input pin is the active low hardware reset from the host.
+5 V, +3.3 V power.
This output signal may be used as IORDY.
This output signal is asserted low when this device is expecting a word data
transfer cycle.
In True IDE Mode signal is the active high Interrupt Request to the host.
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Description
HANBit Electronics Co., Ltd.
HFDOM44P-xxxSx