AM53CF94JCW AMD [Advanced Micro Devices], AM53CF94JCW Datasheet - Page 31

• Manufacturer Part Number: AM53CF94JCW
• Description: Enhanced SCSI-2 Controller (ESC)
• Manufacturer: AMD [Advanced Micro Devices]

Forced Test Mode Register (0AH) Write
The Forced Test Mode Register (FTMREG) is for test
use only. The STE bit in the Control Register One
(CNTLREG1) must be set for the FTMREG to operate.
FTMREG – Bits 7:3 – RES – Reserved
FTMREG – Bit 2 – FHI – Forced High Impedance
Mode
The FHI bit when set places all the output and bidirec-
tional pins into a high impedance state. It is zeroed by a
hardware or chip reset.
FTMREG – Bit 1 – FIM – Forced Initiator Mode
The FIM bit when set forces the ESC into the Initiator
mode. As an Initiator, the device will drive SCSI data
lines, and ACK or ATN (depending on the bus phase and
Control Register Two (0BH) Read/Write
The Control Register Two (CNTLREG2) sets up the de-
vice with various operating parameters.
CNTLREG2 – Bit 7 – DAE – Data Alignment Enable
The DAE bit is used in the Initiator Synchronous Data-In
phase only. When the DAE bit is set one byte is reserved
at the bottom of the FIFO when the phase changes to
the Synchronous Data-In phase. The contents of this
byte will become the lower byte of the DMA word (16-bit)
Control Register Two
CNTLREG2
DAE
7
0
Forced Test Mode Register
FTMREG
ENF
RES
7
x
6
0
RES
SBO
6
x
5
0
TSDR
RES
5
x
4
0
Am53CF94/Am53CF96
P R E L I M I N A R Y
S2FE
RES
4
x
3
0
ACDPE
RES
2
0
3
x
Type: Read/Write
PGRP
FHI
2
0
1
0
the command loaded in the Command Register). The
ESC will remain in this mode for as long as BSY is as-
serted, or until a Reset SCSI Bus or Reset Device com-
mand occurs. During normal operation this bit must not
be set.
FTMREG – Bit 0 – FTM – Forced Target Mode
The FTM bit when set forces the ESC into the Target
mode. As a Target, the device does not assert BSY;
rather, it drives SCSI data lines, REQ, MSG, C/D or I/O
(depending on the command loaded in the Command
Register). The ESC will remain in this mode until a Dis-
connect Steps, Reset SCSI Bus, or Reset Device com-
mand occurs. During normal operation this bit must not
be set.
transferred to the memory, the upper byte being the first
byte of the first word received from the SCSI bus.
Note:
If an interrupt is received for a misaligned boundary on a
phase change to synchronous data the following recov-
ery procedure may be followed. The host processor
should copy the byte at the start address in the host
memory to the Data Alignment Register 0FH (DALREG)
Address: 0B
PGDP
FIM
1
0
0
0
Address: 0A
Type: Write
H
Pass Through/Generate Data Parity
Pass Through/Generate Register Parity
Abort on Command/Data Parity Error
SCSI-2 Features Enable
Tri-State DMA Request
Select Byte Order
Enable Features
Data Alignment Enable
FTM
0
0
H
Forced Target Mode
Forced Initiator Mode
Forced High Impedance Mode
Reserved
Reserved
Reserved
Reserved
Reserved
17348B-30
17348B-31
AMD
31