ISL6615 INTERSIL [Intersil Corporation], ISL6615 Datasheet - Page 8

• Manufacturer Part Number: ISL6615
• Description: High-Frequency 6A Sink Synchronous MOSFET Drivers with Protection Features
• Manufacturer: INTERSIL [Intersil Corporation]

where the gate charge (Q
particular gate to source voltage (V
corresponding MOSFET datasheet; I
quiescent current with no load at both drive outputs; N
and N
respectively; PVCC is the drive voltage for both upper and
lower FETs. The I
the driver without capacitive load and is typically 200mW at
300kHz and VCC = PVCC = 12V.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R
(R
typical upper and lower gate drives turn-on transition path.
The power dissipation on the driver can be roughly
estimated, as shown in Equation 4.
P
P
P
P
R
I
DR
Qg_TOT
DR
DR_UP
DR_LOW
EXT1
GI1
P
P
=
=
Qg_Q2
Qg_Q1
Q2
and R
⎛
⎜
⎝
P
=
Q
-----------------------------------------------------
DR_UP
=
are the number of upper and lower MOSFETs,
G1
=
R
=
⎛
⎜
⎝
G1
G1
P
GI2
--------------------------------------
R
•
=
⎛
⎜
⎝
=
Qg_Q1
HI1
--------------------------------------
R
PVCC N
V
+
and R
Q
-------------------------------------- - F
Q
-------------------------------------- - F
HI2
) of MOSFETs. Figures 3 and 4 show the
+
GS1
R
-------------
R
N
G2
G1
+
Q
P
GI1
HI1
Q1
R
R
+
V
DR_LOW
V
*VCC product is the quiescent power of
•
HI2
+
•
GS2
EXT1
R
GS1
•
G2
PVCC
PVCC
P
EXT2
Qg_Q2
) and the internal gate resistors
Q1
G1
+
+
2
+
2
+
--------------------------------------- -
R
Q
-----------------------------------------------------
•
I
•
and Q
LO1
--------------------------------------- -
R
+
Q
R
8
G2
LO2
EXT2
I
•
SW
Q
SW
R
VCC
•
+
LO1
R
•
PVCC N
+
V
R
LO2
VCC
•
GS1
•
G2
N
GS2
EXT1
R
N
Q
=
) is defined at a
EXT2
Q2
Q1
R
and V
is the driver’s total
G2
•
⎞
⎟
⎠
•
⎞
⎟
⎠
+
Q2
P
---------------------
•
GS2
R
-------------
Qg_Q1
N
P
---------------------
⎞
⎟
⎠
GI2
Q2
Qg_Q2
2
•
2
) in the
F
SW
(EQ. 2)
(EQ. 3)
(EQ. 4)
Q1
+
I
Q
ISL6615
Application Information
Layout Considerations
The parasitic inductances of the PCB and of the power
devices’ packaging (both upper and lower MOSFETs) can
cause serious ringing, exceeding the device’s absolute
maximum ratings. A good layout helps reduce the ringing on
the switching node (PHASE) and significantly lowers the
stress applied to the output drives. The following advice is
meant to lead to an optimized layout and performance:
• Keep decoupling loops (VCC-GND, PVCC-GND and
• Minimize trace inductance, especially on low-impedance
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
BOOT-PHASE) short and wide (at least 25 mils). Avoid
using vias on decoupling components other than their
ground terminals, which should be on a copper plane with
at least two vias.
lines. All power traces (UGATE, PHASE, LGATE, GND,
PVCC, VCC, GND) should be short and wide (at least
25 mils). Try to place power traces on a single layer,
otherwise, two vias on interconnection are preferred
where possible. For no connection (NC) pins on the QFN
part, connect it to the adjacent net (LGATE2/PHASE2) can
reduce trace inductance.
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
PVCC
PHASE
R
R
BOOT
LO2
R
HI2
R
LO1
HI1
R
G2
R
G
G1
G
R
C
GI2
R
GD
C
C
GI1
GD
GS
C
GS
S
S
D
D
Q2
C
April 24, 2008
Q1
DS
C
FN6481.0
DS