LIS302DL_07 STMICROELECTRONICS [STMicroelectronics], LIS302DL_07 Datasheet - Page 13

• Manufacturer Part Number: LIS302DL_07
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

LIS302DL
1. Data based on standard I
2. A device must internally provide an hold time of at least 300ns for the SDA signal (referred to VIHmin of the SCL signal) to
3. Cb = total capacitance of one bus line, in pF
4. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both port
t
t
SCL
r(SDA)
SDA
f(SDA)
bridge the undefined region of the falling edge of SCL
t
Symbol
t
t
t
w(SP:SR)
w(SCLH)
t
w(SCLL)
t
su(SDA)
t
f
h(SDA)
t
su(SR)
su(SP)
(SCL)
h(ST)
t
t
t
r(SCL)
f(SCL)
f(SDA)
2.3.2
Subject to general operating conditions for Vdd and top.
Table 6.
Figure 4.
t
h(ST)
SCL clock frequency
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
Repeated START condition
setup time
STOP condition setup time
Bus free time between STOP
and START condition
START
t
w(SCLL)
t
I
r(SDA)
2
2
C - inter IC control interface
Parameter
C protocol requirement, not tested in production
I
I
2
2
C slave timing values
C slave timing diagram
t
w(SCLH)
t
su(SDA)
t
r(SCL)
I
2
C Standard mode
Min
250
4.7
4.0
4.7
4.7
0
0
4
4
t
f(SCL)
t
h(SDA)
(4)
3.45
1000
Max
Mechanical and electrical specifications
100
300
(2)
(1)
20 + 0.1C
20 + 0.1C
Min
100
1.3
0.6
0.6
0.6
0.6
1.3
I
0
0
2
C Fast mode
t
su(SR)
b
b
t
(3)
(3)
su(SP)
t
w(SP:SR)
0.9
Max
400
300
300
REPEATED
(1)
(2)
START
STOP
START
Unit
13/42
KHz
µs
ns
µs
ns
µs