HYB5116400BJ-50- SIEMENS [Siemens Semiconductor Group], HYB5116400BJ-50- Datasheet

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... Fast page mode capability • All inputs, outputs and clocks fully TTL-compatible • 4096 refresh cycles / 64 ms • Plastic Package: P-SOJ-26/24 300 mil • P TSOPII-26/24 300 mil Semiconductor Group HYB5116400BJ -50/-60/-70 HYB5116400BT -50/-60/-70 -50 -60 - ...

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... P-SOJ-26/24 300 mil DRAM (access time 50 ns) P-SOJ-26/24 300 mil DRAM (access time 60 ns) P-SOJ-26/24 300 mil DRAM (access time 70 ns) P-TSOPII-26/24 300mil DRAM (access time 50 ns) P-TSOPII-26/24 300mil DRAM (access time 60 ns) P-TSOPII-26/24 300mil DRAM (access time 70 ns 4-DRAM ...

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... Pin Configuration Semiconductor Group Vcc RAS A11 6 21 A10 VCC 13 14 P-SOJ-26/24 300 mil P-TSOPII-26/24 300 mil 3 HYB 5116400BJ/BT-50/-60/- 4-DRAM Vss I/O4 I/O3 CAS Vss ...

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... A11 Row 12 Address Buffers(12) No. 1 Clock RAS Generator Block Diagram Semiconductor Group HYB 5116400BJ/BT-50/-60/-70 & Data in Buffer 12 Row 12 Decoder Voltage Down Generator 4-DRAM I/O1 I/O2 I/O3 I/O4 Data out Buffer 4 4 Column 10 Decoder Sense Amplifier I/O Gating 1024 x4 Memory Array 4096 4096x1024x4 VCC VCC (internal ...

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... I CC1 -50 ns version -60 ns version -70 ns version = t min CC2 I CC3 -50 ns version -60 ns version -70 ns version = t min HYB 5116400BJ/BT-50/-60/- 4-DRAM Limit Values Unit Test Condition min. max. 1) 2.4 Vcc+0 – 0.5 0 2.4 – – 0 – ...

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... CC5 I CC6 -60 ns version -70 ns version min.) I CC7 MHz Symbol HYB 5116400BJ/BT-50/-60/- 4-DRAM Limit Values Unit Test min. max. – – – – – 100 mA – – 80 ...

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... OEA 25 – 30 RAL t 0 – 0 RCS 0 – RCH 0 – RRH t 0 – 0 CLZ OFF 4-DRAM Unit Note -60 -70 max. min. max. – 130 – ns – 50 – ns 10k 70 10k ns 10k 20 10k ns – 0 – ns – 10 – ns – 0 – ...

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... CWD 43 – AWD 13 – t OEH t 35 – – – 30 CPA t 50 200k 60 RAS t 30 – RHPC 8 HYB 5116400BJ/BT-50/-60/- 4-DRAM Limit Values -60 -70 max. min. max – 0 – 15 – 20 – 15 – 20 – 10 – 10 – 10 – 10 – 0 – ...

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... WRH 35 – t CPT t 30 – CHRT 10 – t WTS 10 – t WTH 100k – t RASS 95 – t RPS t -50 – CHS 9 HYB 5116400BJ/BT-50/-60/- 4-DRAM Limit Values -60 -70 max. min. max. 80 – 95 – 55 – 65 – 10 – 10 – 10 – 10 – 5 – 5 – 10 – 10 – 10 – ...

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... CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other manner (ROR - Distributed/Burst ...

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... RAS t CSH t t RSH RCD t CAS t RAD t RAL t CAH t ASC Column t t RAH RCS OEA t DZC t DZO t CAC t CLZ RAC 11 HYB 5116400BJ/BT-50/-60/- 4-DRAM CRP t ASR Row t RCH t RRH t CDD t ODD t OFF t OEZ Valid Data Out Hi Z WL1 ...

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... Write Cycle (Early Write) Semiconductor Group RAS t CSH t t RCD RSH t CAS t t RAD RAL t CAH t ASC Column t CWL t RAH t WCS WCH t RWL Valid Data HYB 5116400BJ/BT-50/-60/- 4-DRAM CRP t ASR Row WL2 . ...

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... Write Cycle (OE Controlled Write) Semiconductor Group RAS t CSH t t RCD RSH t CAS t RAD t RAL t CAH t ASC Column t CWL t RAH OEH t ODD t t DZO DZC OEZ Valid Data t CLZ t OEA Hi-Z 13 HYB 5116400BJ/BT-50/-60/- 4-DRAM CRP t ASR Row RWL t DH Hi-Z WL3 . ...

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... RAH CAH t ASC Column t AWD t RAD t CWD t RWD RCS OEA t DZO t DZC t CLZ t CAC Data t RAC 14 HYB 5116400BJ/BT-50/-60/- 4-DRAM RSH t CRP t CAS t ASR t CWL t RWL OEH Valid Data in t ODD t OEZ Out Row WL4 ...

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... OEA t t DZC DZC t DZO t DZO t ODD CAC OFF CAC t RAC t OEZ t t CLZ CLZ Valid Data Out 15 HYB 5116400BJ/BT-50/-60/- 4-DRAM RHCP t CAS RSH t CRP t CAS t CAH t ASC Column t t RCS t RRH t CPA OEA OEA t DZC ...

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... Column t t CWL CWL t WCS t t WCH WCH Valid Valid Data In Data In 16 HYB 5116400BJ/BT-50/-60/- 4-DRAM RSH t CAS t CAS CRP t RAL t t ASR CAH t ASC Column Column t CWL t t RWL WCS t WCH t WP ...

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... Fast Page Mode Read-Modify-Write Cycle Semiconductor Group HYB 5116400BJ/BT-50/-60/- 4-DRAM ...

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... V IH RAS CAS ASR V IH Address I/O (Outputs “H” or “L” RAS-Only Refresh Cycle Semiconductor Group HYB 5116400BJ/BT-50/-60/- RAS t RAH Row HI 4-DRAM CRP t RPC t ASR Row WL9 ...

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... OEZ CDD V IH I/O (Inputs ODD V OH I/O (Outputs OFF “H” or “L” CAS-Before-RAS Refresh Cycle Semiconductor Group t RAS t CSR t CHR t WRP t WRH HI-Z 19 HYB 5116400BJ/BT-50/-60/- 4-DRAM RPC WL10 CRP ...

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... CAS CDD V IH I/O (Inputs ODD t OEZ V OH I/O (Outputs OFF “H” or “L” CAS-before-RAS Self Refresh Semiconductor Group RASS t CSR t WRP t WRH 20 HYB 5116400BJ/BT-50/-60/- 4-DRAM t RPS t CHS HI-Z WL13 t CRP ...

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... RAS t RSH t RCD t t WRP ASC t CAH Column t RRH RCS OEA t DZC t DZO t CAC t CLZ t RAC Valid Data Out 21 HYB 5116400BJ/BT-50/-60/- 4-DRAM RAS t t CRP CHR t t ASR WRH t CDD t ODD t OFF t OEZ HI-Z Row WL11 ...

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... Hidden Refresh Cycle (Early Write) Semiconductor Group RAS t t RCD RSH t RAD t ASC t CAH Column t WCS t t WRP WCH Valid Data HI-Z 22 HYB 5116400BJ/BT-50/-60/- 4-DRAM RAS t t CHR CRP t ASR t WRH WL12 Row ...

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... Semiconductor Group CSR CHR t t ASC Column WRP t t WRH RCS t DZC t DZO t WCS t WRH t DS Data In HI-Z 23 HYB 5116400BJ/BT-50/-60/- 4-DRAM RAS t RSH t CAS t RAL CAH CAC t OEA t CDD t ODD t OFF t t CLZ OEZ Data Out ...

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... OEZ V I/O OH (Outputs “H” or “L” Test Mode Entry Semiconductor Group RAS RPC CSR CP CHR t t RAH ASR Row t t WTS WTH ODD HI-Z t CDD OFF 24 HYB 5116400BJ/BT-50/-60/- 4-DRAM CRP RPC HI-Z WL15 ...

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... M Block A0C,A1C 1 M Block Normal 1 M Block I Block Test 1 M Block Block Diagram in Test Mode Semiconductor Group HYB 5116400BJ/BT-50/-60/-70 A0C,A1C A0C,A1C A0C,A1C A0C,A1C 4-DRAM Vcc Normal I/O 1 Test Vss Vcc Normal I/O 2 Test Vss Vcc Normal I/O 3 Test Vss Vcc Normal ...

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... Package Outlines Plastic Package P-SOJ-26/24 (300 mil) (Small Outline J-leads, SMD) Semiconductor Group HYB 5116400BJ/BT-50/-60/- 4-DRAM ...