COREAES128 ACTEL [Actel Corporation], COREAES128 Datasheet

COREAES128

Manufacturer Part Number

COREAES128

Description

CoreAES128

Manufacturer

ACTEL [Actel Corporation]

Datasheet

1.COREAES128.pdf (13 pages)

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CoreAES128

Product Summary

Intended Use

Key Features

Supported Families

Core Deliverables

December 2005

• Whenever Data is Transmitted Across an Accessible

• E-commerce

• Personal Security Devices

• Bank

• Compliant with FIPS PUB 197

• ECB (Electronic Codebook) Implementation per

• Example Source Code Provided for CBC, CFB, OFB,

• 128-bit Cipher Key

• Encryption and Decryption Possible with the Same

• 44-Clock Cycle Operation to Encrypt or Decrypt

• Pause/Resume

• Provides Redundant Security

• Fusion

• ProASIC3/E

• ProASIC

• Axcelerator

• Evaluation Version

• Netlist Version

Medium (Wires, Wireless, etc.)

Encryption/Decryption Hardware Can Ease the

Load on Servers

Financial Security Is Mandatory

NIST SP 800-38A

and CTR Modes

Core

128 Bits of Data

Encryption or Decryption at Will

– Compiled

– Structural Verilog and VHDL Netlists (with and

Supported in Actel Libero

Environment (IDE)

without I/O Pads) Compatible with the Actel

Designer Software Place-and-Route Tool

PLUS®

Transactions

RTL

Functionality

Simulation

where

Where

Integrated Design

State-of-the-Art

Model

Dedicated

Continue

Fully

v 4 .0

Synthesis and Simulation Support

Core Verification

Contents

General Description ................................................... 2

CoreAES128 Device Requirements ............................ 4

CoreAES128 Verification ............................................ 4

I/O Signal Descriptions ............................................... 4

CoreAES128 Initialization .......................................... 4

CoreAES128 Operation .............................................. 4

Cipher Key Expansion ................................................ 6

Encryption .................................................................. 7

Decryption .................................................................. 8

Pause/Resume ............................................................. 9

Clear/Abort ............................................................... 10

Modes of Operation ................................................ 10

Ordering Information .............................................. 11

Export Restrictions ................................................... 11

List of Changes ......................................................... 12

Datasheet Categories ............................................... 12

• RTL Version

• Actel-Developed Testbench (Verilog and VHDL)

• Synthesis: Synplicity

• Simulation: OVI-Compliant Verilog Simulators and

• Actel-Developed Simulation Testbench Verifies

• User Can Easily Modify Testbench Using Existing

– Compiled

– Verilog and VHDL Core Source Code

– Core Synthesis Scripts

/ FPGA Compiler

Vital-Compliant VHDL Simulators

CoreAES128 against

National Institute of Standards and Technology

(NIST) Website:

http://csrc.nist.gov/encryption/aes/rijndael/

Format to Add Custom Tests

Supported in Actel Libero IDE

RTL

™

/ FPGA Express

, Synopsys

Simulation

Tests

Available on the

(Design Compiler

™

), Exemplar

Model

™

Fully

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