LH5324500 SHARP [Sharp Electrionic Components], LH5324500 Datasheet

no-image

LH5324500

Manufacturer Part Number
LH5324500
Description
CMOS 24M (3M x 8/1.5M x 16) MROM
Manufacturer
SHARP [Sharp Electrionic Components]
Datasheet
LH5324500
FEATURES
DESCRIPTION
ROM organized as 3,145,728
1,572,864
by a BYTE input pin. It is fabricated using silicon-gate
CMOS process technology.
The LH5324500 is a 24M-bit mask-programmable
3,145,728 words
1,572,864 words
Access time: 150 ns (MAX.)
Power consumption:
Static operation
TTL compatible I/O
Three-state outputs
Single +5 V power supply
Package: 44-pin, 600-mil SOP
(Byte mode)
(Word mode)
Operating: 357.5 mW (MAX.)
Standby: 550 W (MAX.)
16 bits (Word mode) that can be selected
8 bit organization
16 bit organization
8 bits (Byte mode) or
PIN CONNECTIONS
44-PIN SOP
CMOS 24M (3M
Figure 1. Pin Connections for SOP Package
GND
A
A
D
NC
CE
OE
D
D
A
A
A
A
A
D
D
D
D
A
A
D
A
17
18
10
11
7
2
3
6
5
4
3
0
0
8
9
2
1
1
14
15
16
19
10
12
13
17
18
20
22
11
21
8
2
3
4
5
6
7
9
1
8/1.5M
40
38
24
23
44
43
42
39
37
36
35
34
33
32
30
29
28
27
26
41
31
25
D
D
D
A
A
A
A
A
A
A
A
A
A
BYTE
GND
D
D
D
D
D
A
V
13
14
7
13
12
20
19
8
9
10
11
12
15
16
15
14
6
5
4
CC
/A
16) MROM
-1
(LSB)
TOP VIEW
5324500-1
1

Related parts for LH5324500

LH5324500 Summary of contents

Page 1

... Static operation TTL compatible I/O Three-state outputs Single +5 V power supply Package: 44-pin, 600-mil SOP DESCRIPTION The LH5324500 is a 24M-bit mask-programmable ROM organized as 3,145,728 8 bits (Byte mode) or 1,572,864 16 bits (Word mode) that can be selected by a BYTE input pin fabricated using silicon-gate CMOS process technology ...

Page 2

... TIMING SENSE AMPLIFIER GENERATOR ADDRESS BUFFER GND -1 CC Figure 2. LH5324500 Block Diagram NOTE SIGNAL GND NC ) when the BYTE pin is set to be LOW in byte mode, and data output (D –1 and A , the data outputs become ‘Unspecified’ ...

Page 3

... OUT 150 – 0 MHz LH5324500 SUPPLY CURRENT Standby ( Operating ( Operating ( Operating ( Operating ( when set to 15 ADDRESS INPUT SUPPLY CURRENT LSB MSB – ...

Page 4

... LH5324500 AC CHARACTERISTICS (V CC PARAMETER SYMBOL Read cycle time t RC Address access time t AA Chip enable access time t ACE Output enable delay time t OE Output hold time CHZ Output floating time t OHZ t AHZ NOTE: 1. This is the time required for the outputs to become high-impedance. ...

Page 5

... AA ACE (NOTE) t ACE (NOTE (NOTE) DATA VALID Figure 3. Byte Mode (BYTE = (NOTE) t ACE (NOTE (NOTE) DATA VALID Figure 4. Word Mode (BYTE = V IH LH5324500 t CHZ t OHZ t OH 5324500 CHZ t OHZ t OH 5324500 ...

Page 6

... LH5324500 NOTE: HI-Z = High impedance. When the address inputs become ‘High’ to both NOTE: HI-Z = High impedance. When the address inputs become ‘High’ to both A 6 HI-Z DATA VALID Figure 5. Byte Mode (BYTE = V ...

Page 7

... MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT ORDERING INFORMATION LH5324500 N Device Type Package Example: LH5324500N (CMOS 24M ( 1.5M x 16) Mask-Programmable ROM, 44-pin, 600-mil SOP) 23 13.40 [0.528] 16.40 [0.646] 13.00 [0.512] 15.60 [0.614] SEE 22 DETAIL 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.275 [0.050] 2.9 [0.114] 3 ...

Related keywords