COREFIR-EV ACTEL [Actel Corporation], COREFIR-EV Datasheet
COREFIR-EV
Related parts for COREFIR-EV
COREFIR-EV Summary of contents
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... CoreFIR Finite Impulse Response (FIR) Filter Generator Product Summary Intended Use • Finite Impulse Response (FIR) Filter for Actel FPGAs Key Features • Core Generator – Executable File Outputs Run-Time Library (RTL) Code and Testbench Based on Input Parameters – Self-Checking – Executable Tests Generated Output against Algorithm • ...
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... CoreFIR Device Utilization and Performance The CoreFIR generates FIR filters with many configurations. data for the generated FIR filters implemented with the configurations listed in page 3 for the Configuration column in Table 1 • CoreFIR Device Utilization and Performance Family Configuration Combinatorial Fusion 1 Fusion ...
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... EQ 4: ntaps 1 nbits_in 1 nbits_in 1 – – ∑ ∑ c[n] x[n][ v3.0 fpga_family coef_fixed All 1 All 1 All 1 AX, RTAX-S, APA 0 All 1 AX, RTAX-S, APA – b x[n][b]2 – ∑ T(X[b]) 0 CoreFIR ...
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... CoreFIR ntaps 1 ∑ where: = T(X[b]) 0 Note that the x[n][b] can only There are 2 RAM or ROM, the FIR computation becomes nbits_in table lookup operations using x[b] and nbits_in–1 additions. Multiplication operations are eliminated. In summary, the FIR computation using DA for one point of FIR requires: ...
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... The CoreFIR is an Actel FPGA-optimized RTL generator that produces a finite impulse response filter. It implements the DA algorithm to eliminate multiplication for faster and smaller designs. The CoreFIR is a generator which utilizes Actel FPGA’s embedded RAM blocks as DA lookup tables (when available) to further reduce the size of the design ...
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... LUT outputs required by the DA algorithm. Multiple accumulators and shifters may be needed to implement a FIR filter with a large number of taps. I/O Signal Description The FIR filter generated by the CoreFIR Generator consists of the I/O signals defined in Table 3 • I/O Signal Description I/O Signal Direction clk ...
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... Figure 3 • I/O Signals CoreFIR Generator Parameters The CoreFIR generates the RTL code for FIR filters with a variety of parameters. These parameters include generic FIR parameters such as number of taps, number of input’s bits, number of coefficients’ bits, and data type, as well as implementation parameters such as FPGA family, use embedded RAMs, system clock rate, and data sampling rate. The CoreFIR supports the variations specified in Table 4 • ...
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... DA LUT is 2 with ntaps. A LUT splitting method, as defined in "Storage and Large Number of Taps" on page effectively reduces the memory usage. The CoreFIR Generator utilizes this method to reduce the memory usage. It usually splits the coefficients into eight or nine taps for each LUT when embedded RAM blocks are available ...
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... EQ sample_ratio = sys_clk_frq/data_rate CoreFIR supports folding when sample_ratio is greater than or equal to nbits_in. The serialized operations of table lookup and addition are done in nbits_in clock cycles of the system clock, and the design is idle during the rest of sample_ratio and nbits_in cycles ...
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... DA LUTs Using FPGA Cells Some Actel FPGA families such as SX-A and RTSX-S do not have an embedded RAM implementation. In this case, the CoreFIR Generator requires that the lookup table be hard-coded as ROM using FPGA cells. This configuration does not need the DA LUT Generator shown in on page 5 ...
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... Clock and Reset Clock The CoreFIR generates a FIR filter design that uses only positive-edge-triggered registers. The entire design is fully synchronized using the positive edge of the input clock clk, including the embedded RAM blocks (when available). Reset The CoreFIR generates a design that uses only one active ...
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... CoreFIR Appendix I: Sample Configuration File The following shows a sample configuration file. module_name firtest nbits_input 8 nbits_coef 5 ntaps 13 tap data_signed 0 fpga_family ax coef_fixed 1 sys_clk_frq 25 sample_ratio 16 module_lang vhdl 1 2 v3.0 ...
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... Ordering Information Order CoreFIR through your local Actel sales representative. Use the following numbering convention when ordering: CoreFIR-XX, where XX is listed in Table Table 5 • Ordering Codes XX Description EV Evaluation Version AR RTL for unlimited use on Actel devices UR RTL for unlimited use and not restricted to Actel devices List of Changes The following table lists critical changes that were made in the current version of the document ...
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Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Corporation Actel Europe Ltd. 2061 Stierlin Court Dunlop House, Riverside Way Mountain View, CA Camberley, Surrey GU15 3YL 94043-4655 ...