GAL6002B-20LJ LATTICE [Lattice Semiconductor], GAL6002B-20LJ Datasheet - Page 14

• Manufacturer Part Number: GAL6002B-20LJ
• Description: High Performance E2CMOS FPLA Generic Array Logic
• Manufacturer: LATTICE [Lattice Semiconductor]

Circuitry within the GAL6002 provides a reset signal to all registers
during power-up. All internal registers will have their Q outputs
set low after a specified time (tpr, 1 s MAX). As a result, the state
on the registered output pins (if they are enabled) will always be
high on power-up, regardless of the programmed polarity of the
output pins. This feature can greatly simplify state machine design
by providing a known state on power-up. The timing diagram for
power-up is shown below. Because of the asynchronous nature
The number of Differential Product Term Switching (DPTS ) for
a given design is calculated by subtracting the total number of
product terms that are switching from a Logical HI to a Logical LO
from those switching from a Logical LO to a Logical HI within a
5ns period. After subtracting take the absolute value.
DPTS restricts the number of product terms that can be switched
simultaneously - there is no limit on the number of product terms
that can be used.
Power-Up Reset
Differential Product Term Switching (DPTS) Applications
DPTS = (P-Terms)
FEEDBACK/EXTERNAL
INTERNAL REGISTER
OUTPUT REGISTER
LH
- (P-Terms)
Q - OUTPUT
CLK
Vcc
HL
Vcc (min.)
14
t
pr
of system power-up, some conditions must be met to provide a
valid power-up reset of the GAL6002. First, the V
monotonic. Second, the clock input must be at static TTL level
as shown in the diagram during power up. The registers will reset
within a maximum of tpr time. As in normal system operation,
avoid clocking the device until all input and feedback path setup
times have been met. The clock must also meet the minimum
pulse width requirements.
The majority of designs fall below 15 DPTS, with the upper limit
being approximately 25 DPTS. Lattice Semiconductor guarantees
and tests the commercial grade GAL6002 for functionality at
DPTS 30.
A software utility is available from Lattice Semiconductor
Applications Engineering that will perform this calculation on any
GAL6002 JEDEC file. This program, DPTS, and additional
information may be obtained from your local Lattice
Semiconductor representative or by contacting Lattice
Semiconductor Applications Engineering Dept. (Tel: [phone]
or 1-888-ISP-PLDS; FAX: [phone]).
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
t
wl
t
su
Specifications GAL6002
CC
rise must be