PM7380-PI PMC [PMC-Sierra, Inc], PM7380-PI Datasheet

PM7380-PI

Manufacturer Part Number

PM7380-PI

Description

FRAME ENGINE AND DATA LINK MANAGER 32P672

Manufacturer

PMC [PMC-Sierra, Inc]

Datasheet

1.PM7380-PI.pdf (2 pages)

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FEATURES

The FREEDM-32P672 chip offers the

following features:

• Single-chip multi-channel HDLC

• An on-chip DMA controller with

• Supports up to 672 bi-directional

BLOCK DIAGRAM

PMC-1980245 (r2)

Frame Engine and Data Link Manager

controller with a 66 MHz, 32-bit

Peripheral Component Interconnect

(PCI) 2.1 compatible bus for

configuration, monitoring, and transfer

of packet data.

scatter/ gather capabilities.

HDLC channels assigned to a

maximum of 32 MVIP digital telephony

buses (at 2.048 Mbit/s per link) or 8

H-MVIP buses (at 8.192 Mbit/s per

link).

HDLC channels assigned to a

maximum of 32 channelized T1/J1 or

E1 links.

RMVCK[3:0]

TMVCK[3:0]

RCLK[31:0]

TCLK[31:0]

RMV8FPC

TMV8FPC

RFPB[3:0]

TFPB[3:0]

RMV8DC

TMV8DC

RD[31:0]

TD[31:0]

RFP8B

TFP8B

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

PMC-Sierra,Inc.

(RCAS672)

(TCAS672)

Assigner

Transmit

Assigner

Receive

Channel

• The number of time-slots assigned to

• Supports up to 32 bi-directional HDLC

• Channels assigned to links 0 to 2

• In the special case, where no more

• Links configured for channelized T1/

(RHDL672)

(THDL672)

an HDLC channel is programmable

from 1 to 24 (for T1/J1) and from 1 to

31 (for E1).

channels, each assigned to an

unchannelized arbitrary-rate link,

subject to a maximum aggregate link

clock-rate of 64 MHz in each direction.

support a clock rate of up to 52 MHz.

Channels assigned to links 3 to 31

support a clock rate of up to 10 MHz.

than three high-speed links are used,

the maximum aggregate link

clock-rate is 156 MHz.

J1/E1 or unchannelized operation

support the gapped-clock method for

determining time-slots, which is

backwards compatible with the

FREEDM-8 and FREEDM-32 devices.

Processor

Transmit

Receive

HDLC

32 k Transmit

32 k Receive

Performance

(PMON)

Monitor

Packet

Partial

Buffer

(RMAC672)

(TMAC672)

Controller

Transmit

Receive

JTAG

DMA

• For each channel, the HDLC receiver

• The receiver supports the validation of

• For each channel, the HDLC

• The transmitter supports the

• The transmitter also aborts packets

• Provides 32 kbytes of on-chip memory

supports programmable

flag-sequence detection, bit

de-stuffing, and frame-check

sequence validation.

both CRC-CCITT and CRC-32

frame-check sequences.

transmitter supports programmable

flag-sequence generation, bit stuffing

and frame-check sequence

generation.

generation of both CRC-CCITT and

CRC-32 frame-check sequences.

under the direction of the host, or

automatically when the channel

underflows.

for partial-packet buffering in both the

transmit and receive directions.

(GPIC672)

Controller

PCI

FREEDM-32P672

AD[31:0]

C/BEB[3:0]

PAR

FRAMEB

TRDYB

IRDYB

STOPB

DEVSELB

IDSEL

LOCKB

REQB

GNTB

PERRB

SERRB

PCIINTB

PCICLK

PCICLKO

M66EN

PM7380

Related parts for PM7380-PI

PM7380-PI Summary of contents

Page 1

... HDLC Partial DMA Processor Packet Controller (THDL672) Buffer (TMAC672) JTAG PM7380 FREEDM-32P672 • For each channel, the HDLC receiver supports programmable flag-sequence detection, bit de-stuffing, and frame-check sequence validation. • The receiver supports the validation of both CRC-CCITT and CRC-32 frame-check sequences. ...

Page 2

... QUAD All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: info@pmc-sierra.com PM7380 FREEDM-32P672 APPLICATIONS Use the FREEDM-32P672 chip in the following applications: • Remote Access Concentrators. • Frame Relay/Multiservice Switches. • Multiservice Access Concentrators. • Internet/Edge Routers. ...

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