AX88615 ASIX [ASIX Electronics Corporation], AX88615 Datasheet - Page 6

• Manufacturer Part Number: AX88615
• Description: 5-Port 10/100BASE Ethernet Switch
• Manufacturer: ASIX [ASIX Electronics Corporation]

2.0 Pin Description
2.0 Pin Description
The following terms describe the AX88615 pinout:
All pin names with the “/” suffix are asserted low.
2.1 MII/RMII interface for switch ports
2.1.1 Switch Port 0
STXEN0
STXD0[3:0]
STXCLK0
SDUPLEX0
SCOL_SP0
SCRS0
or
SCRS_DV0
SRXDV0
SRXCLK0
SRXD0[3:0]
Signal Name
I
O
I/O
AX88615P 5-Port 10/100Mb Switch Controller PRELIMINARY
Type
O
O
I
I
I
I
I
I
I
=
=
=
91,90,89,88 Transmit Data : STXD0[3:0] is synchronous to the rising edge of
Pin No.
114,113,
111,110
104
87
93
94
97
96
98
Input
Output
Input /Output
Transmit Enable : Active HIGH. This output indicates that the packet
is being transmitted .If MII mode, TXEN0 is synchronous to
STXCLK0. If RMII mode, TXEN0 is synchronous to REF_CLK.
STXCLK0 in MII mode. For each STXCLK period in which STXEN is
asserted, TXD[3:0] are accepted for transmission by the PHY.
If RMII mode, STXD0[1:0] is synchronous to REF_CLK. TXD0[1:0]
shall be “00” to indicate idle when TX_EN is disserted. Value that is not
“00” is reserved for out-of-band signaling and shall be ignored by PHY.
When TX_EN is asserted, TXD[1:0] are accepted for transmission by
PHY
Transmit Clock : Provides the timing reference for the STXEN0,
STXD0 signals in MII mode. STXCLK0 frequency is one fourth of the
data rate (25 MHz for 100Mbps, 2.5 MHz for 10Mbps).
Duplex Select : DUPLEX0 is not standard MII/RMII signal. This input
is connected to PHY directly to obtain the current data rate of Port0.
Collision Detect: Active HIGH. Indicates a collision has been detected
on wire in MII mode. This input is not synchronous to any clock and
ignored in full-duplex mode
If RMII mode, the signal is a speed indicator. Active for 10Mbps speed
is selected depending on power on configuration.
Carrier Sense : Active HIGH. Indicates that either the transmit or
receive medium is non-idle in MII mode. SCRS0 is not synchronous to
any clock.
When RMII mode, the input is CRS_DV (Carrier Sense/Receive Data
Valid ) that is asserted asynchronously on detection of carrier by the
PHY when receive medium is non-idle. Loss of carrier shall result in
the desertion of CRS_DV synchronous to the cycle of REF_CLK, which
presents the first DI-bit of a nibble on to RXD0[1:0].
Receive Data Valid : Active HIGH. Indicates that valid data is present
on the SRXD0 lines. Synchronous to SRXCLK0.
Receive Clock : Provides the timing reference for the SRXDV0,
SRXD0 signals in MII mode. STXCLK0 frequency is one fourth of the
data rate (25 MHz for 100Mbps, 2.5 MHz for 10Mbps).
Receive Data : Synchronously to the rising edge of RXCLK in MII
mode.
If RMII mode, SRXD0[1:0] is synchronous to REF_CLK. SRXD0[1:0]
shall be “00” to indicate idle when CRS_DV is disserted. Value that is
not “00” is reserved for out-of-band signaling shall be ignored by MAC
Upon assertion of CRS_DV, PHY shall ensure that RXD[1:0] = “00”
until proper receive decoding takes place
6
Description
ASIX ELECTRONICS CORPORATION
CONFIDENTIAL