9248DF-39 Integrated Device Technology, 9248DF-39 Datasheet - Page 12

• Manufacturer Part Number: 9248DF-39
• Description: ic,9248df-39
• Manufacturer: Integrated Device Technology

CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power
operation. CPU_STOP# is synchronized by the ICS9248-39. The minimum that the CPU clock is enabled (CPU_STOP#
high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks
will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.
CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
0277G—08/04/04
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is
3. IOAPIC output is Stopped Glitch Free by CPUSTOP# going low.
4. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-39
5. All other clocks continue to run undisturbed.
ICS9248-39
synchronized to the CPU clocks inside the ICS9248-39.
CPU_STOP# signal. SDRAM (0:11) are controlled as shown.
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