ADA4096-4ARUZ-RL Analog Devices, ADA4096-4ARUZ-RL Datasheet - Page 16

• Manufacturer Part Number: ADA4096-4ARUZ-RL
• Description: the ada4096-2 dual and ada4096-4 quad operational...
• Manufacturer: Analog Devices

ADA4096-2/ADA4096-4
THEORY OF OPERATION
INPUT STAGE
Figure 50 shows a simplified schematic of the ADA4096-2. The
input stage comprises two differential pairs (Q1 to Q4 and Q5
to Q8) operating in parallel. When the input common-mode
voltage approaches V
its minimum voltage compliance. Conversely, when the input
common-mode voltage approaches V
down as I2 reaches its minimum voltage compliance. This
topology allows for maximum input dynamic range because the
amplifier can function with its inputs at 200 mV outside the rail
(at room temperature).
As with any rail-to-rail input amplifier, V
the two input pairs determines the CMRR of the amplifier. If
the input common-mode voltage range is kept within 1.5 V of
each rail, transitions between the input pairs are avoided, thus
improving the CMRR by approximately 10 dB (see Table 3 and
Table 4).
PHASE INVERSION
Some single-supply amplifiers exhibit phase inversion when
the input signal extends beyond the common-mode voltage
range of the amplifier. When the input devices become saturated,
the inverting and noninverting inputs exchange functions,
causing the output to move in the opposing direction.
V
V
+IN
–IN
CC
CC
EE
− 1.5 V, Q1 to Q4 shut down as I1 reaches
OVP
OVP
D3
D1
D4
D2
EE
+ 1.5 V, Q5 to Q8 shut
OS
Q3
Q1
mismatch between
R1
I1
Figure 50. Simplified Schematic,
Q2
Q4
R2
Q7
Q5
R3
Rev. C | Page 16 of 20
I2
Q6
Q8
R4
C1
Q11
Although phase inversion persists for only as long as the inputs are
saturated, it can be detrimental to applications where the amplifier
is part of a closed-loop system. The ADA409x family is free from
phase inversion over the entire common-mode voltage range,
as well as the overvoltage protected range that is stated in the
Absolute Maximum Ratings section, Table 5. Figure 51 shows
the ADA4096-2 in a unity-gain configuration with the input
signal at ±40 V and the amplifier supplies at ±10 V.
Q9
ADA4096-2
D6
Q15
1
Q13
CH1
R5
Q12
Q10
10.0V
Q14
C2
×1
D8
CH2 10.0V
D7
I3
Figure 51. No Phase Reversal
Q16
T
D9
Q17
D10
R6
R7
D11
Q18
M2.00ms
T
34.20%
Q20
Q19
OUT
A CH1
Data Sheet
–3.6V