FM1608-120-SG Ramtron, FM1608-120-SG Datasheet - Page 2

• Manufacturer Part Number: FM1608-120-SG
• Description: fm1608 series 64 k-bit (8k x 8) 5 v 120 ns parallel...
• Manufacturer: Ramtron

Pin Description
Functional Truth Table
Note: The /OE pin controls only the DQ output buffers.
Rev. 3.3
Dec. 2007
Pin Name
A0-A12
DQ0-7
/CE
/OE
/WE
VDD
VSS
/CE
H
L
L
WE
CE
OE
A0-A12
Supply
Supply
Input
Input
Input
Input
/WE
I/O
I/O
X
X
H
Address
Latch
Pin Description
Address: The 13 address inputs select one of 8,192 bytes in the F-RAM array. The
address value will be latched on the falling edge of /CE.
Data: 8-bit bi-directional data bus for accessing the F-RAM array.
Chip Enable: /CE selects the device when low. Asserting /CE low causes the address
to be latched internally. Address changes that occur after /CE goes low will be
ignored until the next falling edge occurs.
Output Enable: Asserting /OE low causes the FM1608 to drive the data bus when
valid data is available. Deasserting /OE high causes the DQ pins to be tri-stated.
Write Enable: Asserting /WE low causes the FM1608 to write the contents of the
data bus to the address location latched by the falling edge of /CE.
Supply Voltage: 5V
Ground.
Control
Logic
Function
Standby/Precharge
Latch Address (and Begin Write if /WE=low)
Read
Write
A10-A12
A0-A7
A8-A9
Figure 1. Block Diagram
Decoder
Row
8,192 x 8 FRAM Array
Column Decoder
Block Decoder
Bus Driver
I/O Latch
DQ0-7
FM1608
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