8305AGILFT IDT, 8305AGILFT Datasheet

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8305AGILFT

Manufacturer Part Number
8305AGILFT
Description
Clock Drivers & Distribution 1
Manufacturer
IDT
Datasheet

Specifications of 8305AGILFT

Rohs
yes
Part # Aliases
ICS8305AGILFT

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G
The ICS8305I is a low skew, 1-to-4, Differential/LVCMOS-to-
LVCMOS/LVTTL Fanout Buffer. The ICS8305I has selectable
clock inputs that accept either differential or single ended
input levels. The clock enable is internally synchronized to
eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin. Outputs are
forced LOW when the clock is disabled. A separate output
enable pin controls whether the outputs are in the active or
high impedance state.
Guaranteed output and part-to-part skew characteristics make
the ICS8305I ideal for those applications demanding well de-
fined performance and repeatability.
B
8305AGI
LVCMOS_CLK
LOCK
ENERAL
CLK_SEL
CLK_EN
nCLK
CLK
D
OE
IAGRAM
D
ESCRIPTION
0
1
0
1
D
LE
Q
Q0
Q1
Q2
Q3
LVCMOS-
www.idt.com
L
OW
1
F
• 4 LVCMOS/LVTTL outputs
• Selectable differential or LVCMOS/LVTTL clock inputs
• CLK, nCLK pair can accept the following differential
• LVCMOS_CLK supports the following input types:
• Maximum output frequency: 350MHz
• Output skew: 40ps (maximum)
• Part-to-part skew: 700ps (maximum)
• 3.3V core, 3.3V, 2.5V or 1.8V output operating supply
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant
P
S
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
LVCMOS, LVTTL
Additive phase jitter, RMS: 0.04ps (typical)
EATURES
IN
KEW
A
TO
4.4mm x 3.0mm x 0.92mm package body
, 1-
SSIGNMENT
-LVCMOS/LVTTL F
LVCMOS_CLK
TO
CLK_SEL
CLK_EN
-4, M
nCLK
GND
CLK
V
OE
16-Lead TSSOP
DD
ICS8305I
G Package
Top View
ULTIPLEXED
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q0
V
Q1
GND
Q2
V
Q3
GND
DDO
DDO
ANOUT
ICS8305I
D
IFFERENTIAL
REV. B JULY 29, 2010
B
UFFER
/

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8305AGILFT Summary of contents

Page 1

... Additive phase jitter, RMS: 0.04ps (typical) • 3.3V core, 3.3V, 2.5V or 1.8V output operating supply • -40°C to 85°C ambient operating temperature • Lead-Free package fully RoHS compliant SSIGNMENT 4.4mm x 3.0mm x 0.92mm package body Q3 www.idt.com 1 ICS8305I - ULTIPLEXED IFFERENTIAL ANOUT 1 GND ...

Page 2

... www.idt.com 2 ICS8305I - ULTIPLEXED IFFERENTIAL ANOUT . ...

Page 3

... F 1. CLK_EN T D IGURE IMING IAGRAM www.idt.com 3 ICS8305I - ULTIPLEXED IFFERENTIAL B ANOUT ...

Page 4

... V ± www.idt.com 4 ICS8305I - ULTIPLEXED IFFERENTIAL ANOUT 85° ...

Page 5

... www.idt.com 5 ICS8305I - ULTIPLEXED IFFERENTIAL B ANOUT 85° ...

Page 6

... ƒ > www.idt.com 6 ICS8305I - ULTIPLEXED IFFERENTIAL B ANOUT 85° ...

Page 7

... FFSET ROM ARRIER REQUENCY vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. www.idt.com 7 ICS8305I - ULTIPLEXED IFFERENTIAL B ANOUT UFFER Input/Output Additive Phase Jitter at 155.52MHz = 0.04ps typical ...

Page 8

... EST IRCUIT ORE V DD SCOPE nCLK CLK GND C D EST IRCUIT IFFERENTIAL PART 1 Qx PART ART TO ART www.idt.com 8 ICS8305I - ULTIPLEXED IFFERENTIAL B ANOUT NFORMATION SCOPE UTPUT OAD EST IRCUIT Cross Points I L NPUT EVEL V DDO ...

Page 9

... PERIOD UTPUT UTY YCLE ULSE IDTH 8305AGI KEW LVCMOS- -LVCMOS/LVTTL F TO 20% Clock Outputs O R UTPUT ISE ERIOD www.idt.com 9 ICS8305I - ULTIPLEXED IFFERENTIAL B ANOUT 80% 80% 20 ALL IME REV. B JULY 29, 2010 / UFFER ...

Page 10

... For example, if the input DD clock swing is only 2.5V and V and R2/R1 = 0.609. VDD R1 1K CLK V_REF nCLK C1 0. INGLE NDED IGNAL RIVING IFFERENTIAL www.idt.com 10 ICS8305I - ULTIPLEXED IFFERENTIAL B ANOUT UFFER = 3.3V, V_REF should be 1.25V DD I NPUT REV. B JULY 29, 2010 / ...

Page 11

... CLK/ IGURE 3.3V 3.3V LVDS_Driv er CLK nCLK HiPerClockS Input 3D. CLK/ IGURE 3.3V R4 125 CLK nCLK HiPerClockS Input OUPLE www.idt.com 11 ICS8305I - ULTIPLEXED IFFERENTIAL B ANOUT 3. Ohm CLK Ohm nCLK HiPerClockS Input CLK NPUT RIVEN BY 3 ...

Page 12

... GND R6 ICS8305 1K (U1,3) VDD C1 VDD=3.3V 0.1u ICS8305I LVCMOS C O LOCK UTPUT R I ELIABILITY NFORMATION 16 L TSSOP EAD by Velocity (Linear Feet per Minute 137.1°C/W 89.0°C/W www.idt.com 12 ICS8305I - ULTIPLEXED IFFERENTIAL B ANOUT LVCMOS Receiv (U1,11) (U1,15) LVCMOS Receiv 0.1u 0. ...

Page 13

... ° 0 ° Reference Document: JEDEC Publication 95, MO-153 www.idt.com 13 ICS8305I - ULTIPLEXED IFFERENTIAL B ANOUT UFFER m REV. B JULY 29, 2010 / ...

Page 14

... While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications ...

Page 15

... www.idt.com 15 ICS8305I - ULTIPLEXED IFFERENTIAL B ANOUT ...

Page 16

... San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners ...

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