5V2528APGGI IDT, 5V2528APGGI Datasheet

5V2528APGGI

Manufacturer Part Number

5V2528APGGI

Description

Clock Drivers & Distribution 2.5/3.3V PLL Clock Driver

Manufacturer

IDT

Datasheet

1.5V2528PGGI.pdf (7 pages)

Specifications of 5V2528APGGI

Rohs

yes

Part # Aliases

IDT5V2528APGGI

Current page: 1 of 7
Download datasheet (73Kb)

FEATURES:

• Operates at 3.3V V

• 1:10 fanout

• 3-level inputs for output control

• External feedback (FBIN) pin is used to synchronize the

• No external RC network required for PLL loop stability

• Configurable 2.5V or 3.3V LVTTL outputs

• t

• Jitter (peak-to-peak) at 133MHz and 166MHz: ±75ps

• Spread spectrum compatible

• Operating Frequency:

• Available in TSSOP package

DESCRIPTION:

loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency

and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

FUNCTIONAL BLOCK DIAGRAM

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE

IDT5V2528/A

2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER

outputs to the clock input signal

The IDT5V2528 is a high performance, low-skew, low-jitter, phase-lock

− − − − −

2002

Phase Error at 100MHz to 166MHz: ±150ps

A: 25MHz to 167MHz

Std: 25MHz to 140MHz

Integrated Device Technology, Inc.

/AV

G_Ctrl

T_Ctrl

FBIN

CLK

and 2.5V/3.3V V

DDQ

2.5V / 3.3V PHASE-LOCK

LOOP CLOCK DRIVER

ZERO DELAY BUFFER

PLL

SELECT

MODE

The IDT5V2528 inputs, PLL core, Y

the 3.3V V

the ten outputs, up to seven may be configured for 2.5V or 3.3V LVTTL

outputs. The number of 2.5V outputs is controlled by 3-level input signals

G_Ctrl and T_Ctrl, and by connecting the appropriate V

3.3V. The 3-level input signals may be hard-wired to high-mid-low levels.

Output signal duty cycles are adjusted to 50 percent, independent of the duty

cycle at CLK. The outputs can be enabled or disabled via the G_Ctrl input.

When the G_Ctrl input is mid or high, the outputs switch in phase and

frequency with CLK; when the G_Ctrl is low, all outputs (except FB

disabled to the logic-low state.

external RC networks. The loop filter for the PLL is included on-chip,

minimizing component count, board space, and cost.

stabilization time to achieve phase lock of the feedback signal to the

reference signal. This stabilization time is required, following power up and

application of a fixed-frequency, fixed-phase signal at CLK, as well as

following any changes to the PLL reference or feedback signals. The PLL

can be bypassed for test purposes by strapping AV

One bank of ten outputs provide low-skew, low-jitter copies of CLK. Of

Unlike many products containing PLLs, the IDT5V2528 does not require

Because it is based on PLL circuitry, the IDT5V2528 requires a

and AV

power supply pins.

TY0, V

TY1, V

TY2, V

TY3, V

TY4, V

TY5, V

TY6, V

TY7, V

FBOUT, V

Y0, V

Y1, V

INDUSTRIAL TEMPERATURE RANGE

DDQ

pin 21

, Y

pin 4

pin 25

pin 15

pin 11

pin 21

, and FB

IDT5V2528/A

OUT

buffers operate from

JUNE 2003

DDQ

to ground.

pins to 2.5V or

DSC 5971/12

OUT

) are

Related parts for 5V2528APGGI

5V2528APGGI Summary of contents

Page 1

... FUNCTIONAL BLOCK DIAGRAM 28 G_Ctrl 1 T_Ctrl 6 CLK 7 FBIN The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE c 2002 Integrated Device Technology, Inc. 2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER The IDT5V2528 inputs, PLL core, Y the 3. DDQ One bank of ten outputs provide low-skew, low-jitter copies of CLK ...

Page 2

... IDT5V2528/A 2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER PIN CONFIGURATION T_Ctrl 1 GND 2 3 TY0 V 4 DDQ CLK FBIN 7 AGND 8 GND 9 TY7 DDQ TY6 12 TY5 13 GND 14 TSSOP TOP VIEW RECOMMENDED OPERATING RANGE Symbol Description DD ( Power Supply Voltage DD, DDQ (1) V Power Supply Voltage ...

Page 3

... IDT5V2528/A 2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER PIN DESCRIPTION Terminal Name No. Type Description (1) CLK 6 I Clock input FBIN 7 I Feedback input (2) G_Ctrl 28 3-level 3-level input for 2.5V / 3.3V Output Select/ Output bank enable. When G_Ctrl is LOW, all outputs except FBOUT are disabled to a logic-LOW state. When G_Ctrl is MID or HIGH, all outputs are enabled and switch at the same frequency as CLK (see OUTPUT SELECTION table) ...

Page 4

... IDT5V2528/A 2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Symbol Parameter V Input Clamp Voltage IK V Input HIGH Level IH V Input LOW Level IL (2) V Input HIGH Voltage Level IHH (2) V Input MID Voltage Level IMM V Input LOW Voltage Level (2) ILL V Output HIGH Voltage Level OH (3 ...

Page 5

... IDT5V2528/A 2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER INPUT TIMING REQUIREMENTS OVER OPERATING RANGE f Clock frequency CLOCK Input clock duty cycle (1) t Stabilization time LOCK NOTE: 1.Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK ...

Page 6

... IDT5V2528/A 2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER TEST CIRCUIT AND VOLTAGE WAVEFORMS From Output Under Test C =30pF L Test Circuit for 3.3V Outputs Y, TY CLK IDT5V2528/A ( BOUT F BIN ( 500Ω PCB TRACE NOTES: 1. All inputs pulses are supplied by generators having the following characteristics ...

Page 7

... Silver Creek Valley Road San Jose, CA 95138 X Process I -40°C to +85°C (Industrial) PG Thin Shrink Small Outline Package PGG TSSOP - Green 5V2528 2.5V / 3.3V Phase-Lock Loop Clock Driver 5V2528A for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 7 INDUSTRIAL TEMPERATURE RANGE for Tech Support: clockhelp@idt.com ...

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