8S89831AKILFT IDT, 8S89831AKILFT Datasheet

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8S89831AKILFT

Manufacturer Part Number
8S89831AKILFT
Description
Clock Drivers & Distribution 1
Manufacturer
IDT
Datasheet

Specifications of 8S89831AKILFT

Rohs
yes
Part # Aliases
ICS8S89831AKILFT
Block Diagram
V
General Description
and Fibre Channel. The internally terminated differential input and
V
LVHSTL and CML to be easily interfaced to the input with minimal
use of external components. The device also has an output enable
pin which may be useful for system test and debug purposes. The
ICS8S89831I is packaged in a small 3mm x 3mm 16-pin VFQFN
package which makes it ideal for use in space-constrained
applications.
ICS8S89831AKI REVISION A APRIL 26, 2010
REF_AC
HiPerClockS™
REF
ICS
nIN
EN
V
IN
_
T
AC
Pullup
50Ω
50Ω
pin allow other differential signal families such as LVDS,
The ICS8S89831I is a high speed 1-to-4 Differential-
to-LVPECL/ECL Fanout Buffer. The ICS8S89831I is
optimized for high speed and very low output skew,
making it suitable for use in demanding applications
such as SONET, 1 Gigabit and 10 Gigabit Ethernet,
D
Differential LVPECL-To-LVPECL/ECL
Fanout Buffer
Q
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
1
Features
Four LVPECL/ECL outputs
IN, nIN input can accept the following differential input levels:
LVPECL, LVDS, CML, SSTL
50
Output frequency: >2.1GHz
Output skew: 30ps (maximum)
Part-to-part skew: 185ps (maximum)
Additive phase jitter, RMS: 0.31ps (typical)
Propagation Delay: 570ps (maximum)
LVPECL mode operating voltage supply range:
V
ECL mode operating voltage supply range:
V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
CC
CC
= 2.5V±5%, 3.3V±5%, V
= 0V, V
internal input termination to V
Pin Assignment
3mm x 3mm x 0.925mm package body
EE
= -3.3V±5%, -2.5V±5%
nQ1
nQ2
Q1
Q2
16-Lead VFQFN
ICS8S89831I
1
2
3
4
16 15 14 13
K Package
5
Top View
6
EE
©2010 Integrated Device Technology, Inc.
7
= 0V
8
T
12
11
10
9
IN
V
V
nIN
T
REF_AC
ICS8S89831I
DATA SHEET

Related parts for 8S89831AKILFT

8S89831AKILFT Summary of contents

Page 1

Differential LVPECL-To-LVPECL/ECL Fanout Buffer General Description The ICS8S89831I is a high speed 1-to-4 Differential- ICS to-LVPECL/ECL Fanout Buffer. The ICS8S89831I is optimized for high speed and very low output skew, HiPerClockS™ making it suitable for use in demanding applications such ...

Page 2

ICS8S89831I Data Sheet Table 1. Pin Descriptions Number Name 1, 2 Q1, nQ1 Output 3, 4 Q2, nQ2 Output 5, 6 Q3, nQ3 Output Power Input 9 nIN Input 10 V Output REF_AC 11 ...

Page 3

ICS8S89831I Data Sheet Function Tables Table 3A. Control Input Function Table Input Outputs EN Q0:Q3 0 Disabled; LOW 1 Enabled NOTE: After EN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in ...

Page 4

ICS8S89831I Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those ...

Page 5

ICS8S89831I Data Sheet Table 4C. Differential DC Characteristics, V Symbol Parameter R Differential Input Resistance IN V Input High Voltage IH V Input Low Voltage IL V Input Voltage Swing IN V Differential Input Voltage Swing DIFF_IN I Input Current; ...

Page 6

ICS8S89831I Data Sheet AC Electrical Characteristics Table 5. AC Characteristics -40°C to 85°C A Symbol Parameter f Output Frequency MAX Propagation Delay; (Differential NOTE 1 tsk(o) Output Skew; NOTE 2, 4 tsk(pp) Part-to-Part Skew; ...

Page 7

ICS8S89831I Data Sheet Parameter Measurement Information LVPECL V EE -0.375V to -1.465V Output Load AC Test Circuit Par t 1 nQx Qx Par t 2 nQy Qy tsk(pp) Part-to-Part Skew OUT 800mV (typical) ...

Page 8

ICS8S89831I Data Sheet Parameter Measurement Information, continued nIN SET-UP HOLD Setup & Hold Time Application Information Recommendations for Unused Output Pins Outputs: LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there ...

Page 9

ICS8S89831I Data Sheet 3.3V Differential Input with Built-In 50 The IN /nIN with built-in 50Ω terminations accept LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both signals must meet the V and V input requirements. Figures ...

Page 10

ICS8S89831I Data Sheet 2.5V LVPECL Input with Built-In 50 The IN /nIN with built-in 50Ω terminations accept LVDS, LVPECL, CML, SSTL and other differential signals. Both signals must meet the V and V input requirements. Figures show ...

Page 11

ICS8S89831I Data Sheet Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that ...

Page 12

ICS8S89831I Data Sheet Termination for 2.5V LVPECL Outputs Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω – 2V. For V = 2.5V, the ...

Page 13

ICS8S89831I Data Sheet VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of ...

Page 14

ICS8S89831I Data Sheet Schematic Example Figure 7 shows a schematic example of the ICS8S89831I. This schematic provides examples of input and output handling. The ICS8S89831I input has built-in 50Ω termination resistors. The input can directly accept various types of differential ...

Page 15

ICS8S89831I Data Sheet Power Considerations This section provides information on power dissipation and junction temperature for the ICS8S89831I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8S89831I is the sum of the ...

Page 16

ICS8S89831I Data Sheet 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pairs. The LVPECL output driver circuit and termination are shown in Figure Figure 8. ...

Page 17

ICS8S89831I Data Sheet Reliability Information Table 7. θ vs. Air Flow Table for a 16 Lead VFQFN JA Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ICS8S89831I is: 328 This device is pin ...

Page 18

ICS8S89831I Data Sheet Package Outline and Package Dimensions Package Outline - K Suffix for 16 Lead VFQFN Seating Plan Index rea N Singulation Singulation Top View D Chamfer 4x 0.6 x 0.6 max OPTIONAL Bottom View w/Type ...

Page 19

... Marking 8S89831AKILF 831A 8S89831AKILFT 831A NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use ...

Page 20

ICS8S89831I Data Sheet Revision History Sheet Rev Table Page Description of Change 11 Deleted Differential Input with Built-in 50 section. This section does not apply when there is only one input Power Considerations - in Power Dissipation section, ...

Page 21

... IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT ...

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