MAX1034BEUG+ Maxim Integrated, MAX1034BEUG+ Datasheet - Page 3

• Manufacturer Part Number: MAX1034BEUG+
• Description: Analog to Digital Converters - ADC 8-/4-Channel, Multirange Inputs,
• Manufacturer: Maxim Integrated

Specifications of MAX1034BEUG+

• Rohs: yes
• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 115 kSPs
• Resolution: 14 bit
• Input Type: Single-Ended/Differential
• Snr: 84.5 dB
• Interface Type: 3-Wire, QSPI, SPI
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-24
• Maximum Power Dissipation: 1111.1 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.136 V

ELECTRICAL CHARACTERISTICS (continued)
(V
external clock mode, V
C
DYNAMIC SPECIFICATIONS f
Signal-to-Noise Plus Distortion
Signal-to-Noise Ratio
Total Harmonic Distortion
(Up to the 5th Harmonic)
Spurious-Free Dynamic Range
Aperture Delay
Aperture Jitter
Channel-to-Channel Isolation
CONVERSION RATE
Byte-Wide Throughput Rate
ANALOG INPUTS (CH0–CH3 MAX1035, CH0–CH7 MAX1034, AGND1)
Small-Signal Bandwidth
Full-Power Bandwidth
Input Voltage Range (Table 6)
True-Differential Analog
Common-Mode Voltage Range
Common-Mode Rejection Ratio
Input Current
Input Capacitance
Input Resistance
DOUT
AVDD1
= 50pF, C
= V
PARAMETER
AVDD2
SSTRB
= V
_______________________________________________________________________________________
REF
DVDD
= 50pF, T
= 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (±V
8-/4-Channel, ±V
= V
DVDDO
IN(SINE-WAVE)
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
SYMBOL
= 5V, V
f
V
SINAD
SAMPLE
CMRR
SFDR
C
V
R
SNR
THD
CMDR
I
t
CH_
t
CH_
CH_
AD
CH_
AJ
AGND1
= 5kHz, V
Differential inputs, FSR = 2 x V
Single-ended inputs, FSR = V
Single-ended inputs, FSR = V
Single-ended inputs, FSR = V
Differential inputs, FSR = 2 x V
Single-ended inputs, FSR = V
Single-ended inputs, FSR = V
Single-ended inputs, FSR = V
Figure 21
Figure 21
External clock mode, Figure 2
External acquisition mode, Figure 3
Internal clock mode, Figure 4
All input ranges, V
All input ranges, V
R[2:1] = 001
R[2:1] = 010
R[2:1] = 011
R[2:1] = 100
R[2:1] = 101
R[2:1] = 110
R[2:1] = 111
DIF/SGL = 1 (Note 4)
DIF/SGL = 1, input voltage range = ±V
-V
REF
= V
DGND
< V
IN
= FSR - 0.05dB, f
CH_
= V
< +V
CONDITIONS
DGNDO
IN
IN
REF
= 100mV
= 4V
REF
= V
P-P
AGND2
SAMPLE
(Note 2)
REF
REF
REF
REF
REF
REF
P-P
REF
REF
Serial 14-Bit ADCs
Multirange Inputs,
/2
/4
/2
/4
= V
(Note 2)
= 130ksps (Notes 1, 2)
AGND3
REF
/4
= 0V, f
-V
-V
-V
A
-V
-V
-1500
-4.75
MIN
REF
REF
REF
= +25°C.)
79
92
REF
REF
0
0
CLK
/4
/2
/2
= 3.5MHz (50% duty cycle),
TYP
84.5
82.5
80.5
84.5
82.5
80.5
100
105
700
-98
84
84
99
15
75
2
5
6
+V
+V
+V
+V
+V
+5.50
+650
MAX
114
106
REF
REF
REF
84
0
0
REF
REF
/4
/2
/2
UNITS
ksps
MHz
kHz
dB
dB
dB
dB
dB
dB
kΩ
ns
ps
µA
pF
V
V
REF
3
),