CDK1301ITQ44 Cadeka Microcircuits, CDK1301ITQ44 Datasheet
CDK1301ITQ44
Specifications of CDK1301ITQ44
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CDK1301ITQ44 Summary of contents
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... Projection display systems n Ordering Information Part Number Package CDK1301ITQ44 TQFP-44 CDK1301ITQ44_Q TQFP-44 Moisture sensitivity level for all parts is MSL-1. ©2008 CADEKA Microcircuits LLC General Description The CDK1301 is a high-speed, 8-bit analog-to-digital converter implemented in an advanced BiCMOS process performance-enhanced version of the CDK1300, offering better linearity and dynamic performance ...
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... +3V/+5V digital output supply DD 1, 33, 34, AGND Analog ground 38, 41 18, 29 DGND Digital ground ©2008 CADEKA Microcircuits LLC ; 100k pullup 100k pullup and 7.5k pulldown to AGND, internally cc = 0); 100k pulldown to AGND, internally DMODE DMODE = 1: interleaved dual channel output ...
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... Parameter Supply Voltage Input Voltages Analog inputs Digital inputs Reliability Information Parameter Storage Temperature Range Recommended Operating Conditions Parameter Operating Temperature Range ©2008 CADEKA Microcircuits LLC Min Max +6 +6 -0.5V V +0.5V cc -0.5V V +0.5V cc Min Typ Max ...
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... SNR Signal-to-Noise Ratio THD Total Harmonic Distortion SINAD Signal-to-Noise and Distortion notes: 1. 100% production tested at +25°C. 2. Parameter is guaranteed (but not tested) by design and characterization data. ©2008 CADEKA Microcircuits LLC = +5V, ƒ = 250MHz, 50% duty cycle, DD clk conditions +25°C, ƒ = 1KHz (1) IN -40° ...
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... Logic “0“ Voltage ( Data DCLK R F notes: 1. 100% production tested at +25°C. 2. Parameter is guaranteed (but not tested) by design and characterization data. ©2008 CADEKA Microcircuits LLC = +5V, ƒ = 250MHz, 50% duty cycle, DD clk conditions +25° 3.0V, 10pF load ±50µA OUT (2) (2) ...
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... DLE vs 0.7 0.6 ƒ = 70.1MHz IN 0.5 ƒ = 250 MSPS S 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 4.5 4.6 4.7 4.8 4.9 5.0 5.1 Volts (V) SNR, SINAD vs. Sample Rate 200 225 Sample Rate (MSPS) ©2008 CADEKA Microcircuits LLC = +5V, ƒ = 250MHz, 50% duty cycle, DD clk 0.8 0.7 ƒ = 70.1 MHz IN 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 250 260 100 5.2 5.3 5.4 5.5 -30 -35 ƒ ...
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... Duty Cycle (%) SNR, SINAD vs SNR 45 SINAD 4.5 4.6 4.7 4.8 4.9 5.0 5.1 Volts (V) ©2008 CADEKA Microcircuits LLC = +5V, ƒ = 250MHz, 50% duty cycle, DD clk -30 ƒ = 70.1 MHz IN -35 ƒ = 250 MSPS S -40 SNR -45 SINAD -50 -55 -60 -65 - 100 -30 ƒ = 70.1 MHz IN -35 ƒ ...
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... MSBs. The digital decode consists of comparators, exclusive of ©2008 CADEKA Microcircuits LLC cells for gray to binary decoding, and/or cells used for mostly over/under range logic. There is a total of 2.5 clock cycles latency before the output bank selection. In ...
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... Data Sheet ©2008 CADEKA Microcircuits LLC Figure 2. Dual Mode Timing Diagram 9 www.cadeka.com ...
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... CDK1301 in nor- mal circuit operation. The following sections provide descriptions of the major functions and outline performance criteria to consider for achieving the optimal device performance. ©2008 CADEKA Microcircuits LLC CDK1301 Figure 3. Typical Interface Circuit Figure 5. Analog Input Equivalent Circuit Analog Input ...
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... PD. When pin PD is set high, the CDK1301 enters the power-down mode. All outputs are set to high impedance. In the powerdown mode the CDK1301 dissipates 24mW typically. ©2008 CADEKA Microcircuits LLC Common-Mode Voltage Reference Circuit The CDK1301 has an on-board common-mode voltage reference circuit (V ) ...
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... CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright ©2008 by CADEKA Microcircuits LLC. All rights reserved. (1:1). An application note (TBD) describing the operation of this board, as well as information on the testing of the CDK1301, is also available ...