MAX11045ECB+ Maxim Integrated, MAX11045ECB+ Datasheet - Page 17

• Manufacturer Part Number: MAX11045ECB+
• Description: Analog to Digital Converters - ADC 16Bit 6Ch Simult Sampling
• Manufacturer: Maxim Integrated

Specifications of MAX11045ECB+

• Rohs: yes
• Number Of Channels: 6
• Architecture: SAR
• Conversion Rate: 250 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended
• Snr: 92.3 dB
• Interface Type: Parallel
• Operating Supply Voltage: 2.7 V to 5.25 V, 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-64
• Maximum Power Dissipation: 3478 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 6
• Voltage Reference: 4.096 V

where V
source produces during a fault condition.
Figures 2 and 3 illustrate the clamp circuit voltage-cur-
rent characteristics for a source impedance R
1280Ω. While the input voltage is within the ±(V
300mV) range, no current flows in the input clamps.
Once the input voltage goes beyond this voltage range,
the clamps turn on and limit the voltage at the input pin.
The bidirectional, parallel, digital interface, CR0–CR3,
sets the 4-bit configuration register. This interface con-
figures the following control signals: chip select (CS),
read (RD), write (WR), end of conversion (EOC), and
convert start (CONVST). Figures 6 and 7 and the
Timing Characteristics in the Electrical Characteristics
table show the operation of the interface.
DB0–DB15/DB13 output the 16-/14-bit conversion result.
All bits are high impedance when RD = 1 or CS = 1.
CR3 selects the internal or external reference. The POR
default = 0.
0 = internal reference, REFIO internally driven through a
10kΩ resistor, bypass with 0.1µF capacitor to AGND.
1 = external reference, drive REFIO with a high-quality
reference.
Figure 2. Input Clamp Characteristics
Maxim Integrated
FAULT_MAX
-10
-20
-30
30
20
10
0
-50
R
R
S
V
Applications Information
S
AVDD
SIGNAL VOLTAGE AT SOURCE AND PIN (V)
= 1280Ω
=
AT CH_ INPUT
-30
= 5V
V
FAULT MAX
is the maximum voltage that the
-10
20
_
mA
CR3 (Int/Ext Reference)
10
- 7
Digital Interface
AT SOURCE
V
30
50
Simultaneous-Sampling ADCs
MAX11044/MAX11045/MAX11046/
AVDD
MAX11054/MAX11055/MAX11056
S
4-/6-/8-Channel, 16-/14-Bit,
=
+
CR2 selects the output data format. The POR default = 0.
0 = offset binary.
1 = two’s complement.
CR1 must be set to 0.
CR0 selects the acquisition mode. The POR default = 0.
0 = CONVST controls the acquisition and conversion.
Drive CONVST low to start acquisition. The rising edge
of CONVST begins the conversion.
1 = acquisition mode starts as soon as the previous
conversion is complete. The rising edge of CONVST
begins the conversion.
To program the configuration register, bring the CS and
WR low and apply the required configuration data on
CR3–CR0 of the bus and then raise WR once to save
changes.
CAUTION: When the configuration register is not
being programmed, the host driving CR3–CR0 must
relinquish the bus when the conversion results of
the ADC are being read!
Figure 3. Input Clamp Characteristics (Zoom In)
Table 1. Configuration Register
Reference
Int/Ext
CR3
-10
-20
-30
Programming the Configuration Register
30
20
10
0
-8
Data Format
R
V
AT SOURCE
S
AVDD
SIGNAL VOLTAGE AT SOURCE AND PIN (V)
Output
= 1280Ω
-6
CR2
= 5V
-4
-2
CR2 (Output Data Format)
0
Must be set
AT CH_ INPUT
CR1
2
to 0
CR0 (CONVST Mode)
4
CR1 (Reserved)
6
8
CONVST
Mode
CR0
17