MAX11629EEE+T Maxim Integrated, MAX11629EEE+T Datasheet
MAX11629EEE+T
Specifications of MAX11629EEE+T
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MAX11629EEE+T Summary of contents
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... System Supervision Data-Acquisition Systems Industrial Control Systems Patient Monitoring Data Logging Instrumentation AutoShutdown is a trademark of Maxim Integrated Products, Inc. QSPI is a trademark of Motorola, Inc. MICROWIRE is a registered trademark of National Semiconductor Corp. Pin Configurations TOP VIEW + AIN0 1 AIN1 ...
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ADCs with FIFO and Internal Reference ABSOLUTE MAXIMUM RATINGS V to GND ..............................................................-0.3V to +6V DD CS, SCLK, DIN, EOC, DOUT to GND.........-0. AIN0–AIN13, AIN_, CNVST/AIN_, REF to GND ...........................................-0. Maximum Current into Any ...
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ELECTRICAL CHARACTERISTICS (continued +2.7V to +3.6V (MAX11627/MAX11629/MAX11633 300kHz 4.8MHz external clock (50% duty cycle), V SCLK (MAX11626/MAX11628/MAX11632 PARAMETER SYMBOL CONVERSION RATE Power-Up Time Acquisition Time Conversion Time External Clock Frequency Aperture Delay ...
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ADCs with FIFO and Internal Reference ELECTRICAL CHARACTERISTICS (continued +2.7V to +3.6V (MAX11627/MAX11629/MAX11633 300kHz 4.8MHz external clock (50% duty cycle), V SCLK (MAX11626/MAX11628/MAX11632 PARAMETER SYMBOL DIGITAL INPUTS (SCLK, ...
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TIMING CHARACTERISTICS (Figure +2.7V to +3.6V (MAX11627/MAX11629/MAX11633 300kHz 4.8MHz (50% duty cycle), V SCLK MAX11628/MAX11632 MIN PARAMETER SYMBOL SCLK Clock Period SCLK Pulse Width High SCLK Pulse ...
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ADCs with FIFO and Internal Reference V = +5V +4.096V 4.8MHz REF SCLK V = +3V +2.5V 4.8MHz REF SCLK DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE 1.0 ...
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V = +5V +4.096V 4.8MHz REF SCLK V = +3V +2.5V 4.8MHz REF SCLK SUPPLY CURRENT vs. SUPPLY VOLTAGE 2000 1800 INTERNAL REFERENCE 1600 1400 1200 EXTERNAL REFERENCE ...
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ADCs with FIFO and Internal Reference V = +5V +4.096V 4.8MHz REF SCLK V = +3V +2.5V 4.8MHz REF SCLK SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE 1.0 ...
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V = +5V +4.096V 4.8MHz REF SCLK V = +3V +2.5V 4.8MHz REF SCLK GAIN ERROR vs. SUPPLY VOLTAGE 0.7 0.6 0.5 0.4 0.3 0.2 0.1 MAX11626/MAX11628/MAX11632 f ...
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ADCs with FIFO and Internal Reference MAX11626 MAX11628 MAX11627 MAX11629 (4 CHANNELS) (8 CHANNELS — — — — 1–7 1–4 — — — — — ...
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CS t CSS0 t CL SCLK DIN t DOE DOUT Figure 1. Detailed Serial-Interface Timing Diagram CS DIN SCLK CNVST AIN1 AIN2 AIN15 REF Figure 2. Functional Diagram Detailed Description The MAX11626–MAX11629/MAX11632/MAX11633 are low-power, serial-output, multichannel ...
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ADCs with FIFO and Internal Reference Converter Operation The MAX11626–MAX11629/MAX11632/MAX11633 ADCs use a successive-approximation register (SAR) conversion technique and an on-chip T/H block to con- vert voltage signals into a 12-bit digital result. This sin- gle-ended configuration supports ...
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True Differential Analog Input T/H The equivalent circuit of Figure 3 shows the MAX11626–MAX11629/MAX11632/MAX11633’s input architecture. In track mode, a positive input capacitor is connected to AIN0–AIN15. A negative input capacitor is connected to GND. For external T/H timing, use ...
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ADCs with FIFO and Internal Reference Conversion Register Select active analog input channels per scan and scan modes by writing to the conversion register. Table 2 details channel selection and the four scan modes. Request a scan by ...
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Table 3. Setup Register* BIT NAME BIT — 7 (MSB) Set select setup register. — 6 Set select setup register. Clock mode and CNVST configuration. Resets power-up. CKSEL1 5 Clock mode ...
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ADCs with FIFO and Internal Reference Table 4. Averaging Register* BIT NAME BIT — 7 (MSB) Set select averaging register. — 6 Set select averaging register. — 5 Set ...
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Power-Up Default State The MAX11626–MAX11629/MAX11632/MAX11633 power up with all blocks in shutdown, including the ref- erence. All registers power up in state 00000000, except for the setup register, which powers up in clock mode 10 (CKSEL1 = 1) Output Data ...
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ADCs with FIFO and Internal Reference CNVST (ACQUISITION1) (ACQUISITION2) CS (CONVERSION1) SCLK DOUT EOC REQUEST MULTIPLE CONVERSIONS BY SETTING CNVST LOW FOR EACH CONVERSION. Figure 5. Clock Mode 01 Timing (CONVERSION BYTE) DIN CS SCLK DOUT EOC THE ...
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DIN (ACQUISITION1) CS SCLK DOUT EOC EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST. Figure 7. Clock Mode 11 Timing Initiate a conversion by writing a byte to the conversion register followed by 16 SCLK cycles pulsed ...
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ADCs with FIFO and Internal Reference Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line ...
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FIFO and Internal Reference Pin Configurations (continued) TOP VIEW + AIN0 1 24 EOC AIN1 2 23 DOUT AIN2 3 22 DIN AIN3 4 21 SCLK MAX11632 AIN4 MAX11633 AIN5 AIN6 7 18 ...
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... Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. 22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2011 Maxim Integrated Products DESCRIPTION Maxim is a registered trademark of Maxim Integrated Products, Inc ...