SSTUM32865ET/G,518 NXP Semiconductors, SSTUM32865ET/G,518 Datasheet
SSTUM32865ET/G,518
Specifications of SSTUM32865ET/G,518
SSTUM32865ET/G-T
SSTUM32865ET/G-T
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SSTUM32865ET/G,518 Summary of contents
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Memory interfaces Support logic for memory modules and other memory subsystems ...
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Portfolio overview PC100 to PC133 DDR200 to DDR266 DDR333 to DDR400 DDR2-400 to DDR2-533 DDR2-667 to DDR2-800 Bus switches Specialty memory solutions Evolution of memory technology 933 800 667 533 400 FPM, 267 EDO 133 0 1995 Memory interfaces 2 ...
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Enabling bandwidth The past decade has seen dramatic changes in memory technology. Moving from SDRAM to DDR and DDR2, new process technologies and improvements in design effi ciency have led to dramatic increases in capacity and speed result, ...
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NXP memory-interface solutions PC 100/PC133 PLL Output enable 1 Clock in PLL Feedback clock 100/PC133 registed driver Output enable Clock Latch enable Data the 17 other channels Memory interfaces PC100 – ...
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NG-DIMM NG-DIMM (Next-generation DIMM proprietary memory- module technology used in servers and workstations. Like the PC100 and PC133 memory modules based on SDR clocking and a 3.3-V supply voltage. Unlike the PC100 and PC133, however, it ...
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NXP memory-interface solutions DDR PLL Power down 1 Differential clock in PLL Differential feedback in N N+1 DDR register 51 Reset REF To other channels Memory interfaces DDR ...
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DDR 333 – 400 The higher speed grades of DDR 333-400 (333 and 400 MT/s, using 167 and 200 MHz clock rates) mean tighter timing specifications – especially register propagation delay, PLL jitter, and skew – to support the shorter ...
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NXP memory-interface solutions DDR2 PLL Control Powerdown control 1 Differential clock in PLL Differential feedback in N N+1 DDR register Reset REF DCKE DODT DCS CSR D1 0 ...
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DDR2 667 The 667 MT/s speed node of DDR2 uses a wider variety of register types with more tightly specified propagation delay times and higher typical operating frequency result, DDR2 667 applications need PLLs with tighter jitter, skew, ...
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NXP memory-interface solutions Memory interfaces 10 DDR2 800 The 800 MT/s speed node of DDR2 – designated by JEDEC standard nomenclature with a ‘B’ in the PLL and register part number – features registers with the lowest absolute propagation delay ...
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DDR Bus Switches CBTV bus switches are typically used to expand total memory capacity in a system by providing a switchable, low-impedance path to multiple memory banks while providing high bus isolation to the remaining banks. The 1:2 switches provide ...
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PLL clock buffers PCK2509SA 3 150 LVTTL PCK2509SL 3 150 LVTTL PCK2510SA 3 150 LVTTL PCK2510SL 3 150 LVTTL PCK2057 2 190 SSTL-2 PCK857 2. 167 SSTL-2 3.3 ...
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Parametric selection tables Bus switches – DDR CBTU4411 1.8 800 11 44 CBTV4010 2.5 400 10 40 CBTV4011 2.5 400 10 40 CBTV4012 2.5 400 10 40 CBTV4020 2.5 400 +85 400-Ω pull-down resistors; ...
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Registers – SDRAM technology 74ALVC16334A 1.2 to 3.6 350 16 74ALVC162334A 1.2 to 3.6 240 16 74ALVC16834A 1.2 to 3.6 350 18 74ALVC162834A 1.2 to 3.6 240 18 74ALVC16835A 1.2 to 3.6 350 18 74ALVC162835A 1.2 to 3.6 240 18 ...
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Registers – DDR and DDR2 technology SSTL16857 2.5; 200 14 x SSTL-2 3.3 SSTL16877 2.5 200 14 x SSTL-2 SSTV16857 2.5 200 14 x SSTL-2 SSTV16857A 2.5 200 14 x SSTL-2 SSTV16859 2.5 200 13 x SSTL-2 SSTVF16857 2.5 210 ...
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