SSTU32865ET/G,557 NXP Semiconductors, SSTU32865ET/G,557 Datasheet - Page 17

• Manufacturer Part Number: SSTU32865ET/G,557
• Description: IC REG BUFFER 28BIT 160-TFBGA
• Manufacturer: NXP Semiconductors

Specifications of SSTU32865ET/G,557

• Logic Type: 1:2 Registered Buffer with Parity
• Supply Voltage: 1.7 V ~ 1.9 V
• Number Of Bits: 28
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-2053; 935275433557; SSTU32865ET/G

Philips Semiconductors
Table 9:
Over recommended operating conditions, unless otherwise noted.
[1]
[2]
[3]
Table 10:
Over recommended operating conditions, unless otherwise noted.
[1]
[2]
Table 11:
Over recommended operating conditions, unless otherwise noted.
9397 750 13799
Product data sheet
Symbol
f
t
t
t
t
t
Symbol
f
t
t
t
t
t
t
Symbol
dV/dt_r
dV/dt_f
dV/dt_
clock
W
ACT
INACT
su
h
MAX
PDM
LH
HL
PLH
PDMSS
PHL
This parameter is not necessarily production tested.
Data inputs must be active below a minimum time of t
Data and clock inputs must be held at valid levels (not floating) a minimum time of t
Includes 350 ps of test-load transmission line delay.
This parameter is not necessarily production tested.
Timing requirements
Switching characteristics
Output edge rates
Parameter
clock frequency
pulse duration, CK, CK HIGH or
LOW
differential inputs active time
differential inputs inactive time
setup time, Chip Select
setup time, Data
setup time, PARIN
hold time
hold time, PARIN
Parameter
maximum input clock frequency
propagation delay
LOW-to-HIGH delay
HIGH-to-LOW delay
LOW-to-HIGH propagation delay
propagation delay, simultaneous
switching
propagation delay
Parameter
rising edge slew rate
falling edge slew rate
absolute difference between dV/dt_r
and dV/dt_f
Rev. 02 — 28 September 2004
Conditions
DCS0, DCS1 valid before
clock switching
Dn valid before clock
switching
PARIN before CK and CK
input to remain valid after
clock switching
PARIN after CK and CK
Conditions
CK and CK to output
CK and CK to PTYERR
CK and CK to PTYERR
from RESET to PTYERR
CK and CK to output
RESET to output
Conditions
ACT(max)
after RESET is taken HIGH.
INACT(max)
1.8 V DDR registered buffer with parity
[1] [2]
[1] [3]
[1] [2]
[1]
after RESET is taken LOW.
Min
-
1
-
-
0.7
0.5
0.5
0.5
0.5
Min
450
1.41
1.2
1
-
-
-
Min
1
1
-
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Typ
-
-
-
-
-
-
-
-
-
Typ
-
-
-
-
-
-
-
Typ
-
-
-
SSTU32865
Max
450
-
10
15
-
-
-
-
-
Max
-
1.8
3
3
3
2.0
3
Max
4
4
1
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Unit
MHz
ns
ns
ns
ns
ns
ns
Unit
V/ns
V/ns
V/ns
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