SSTVA16859BKLFT IDT, Integrated Device Technology Inc, SSTVA16859BKLFT Datasheet - Page 7

• Manufacturer Part Number: SSTVA16859BKLFT
• Description: IC BUFFER DDR 13-26BIT 56VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTVA16859BKLFT

• Logic Type: 13-Bit to 26-Bit Registered Buffer, DDR
• Supply Voltage: 2.3 V ~ 2.7 V
• Number Of Bits: 13, 26
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VFQFN, 56-VFQFPN
• Logic Family: SSTV
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Inputs: 13
• Number Of Outputs: 26
• High Level Output Current: -16mA
• Low Level Output Current: 16mA
• Propagation Delay Time: 3.5ns
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 210(Min)MHz
• Mounting: Surface Mount
• Pin Count: 56
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ / ICS™ DDR 13-Bit to 26-Bit Registered Buffer
ICSSSTVA16859B
DDR 13-Bit to 26-Bit Registered Buffer
1050A—01/07/05
(over recommended operating free-air temperature range, unless otherwise noted)
Notes:
(over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1)
(over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1)
Timing Requirements
Switching Characteristics - DDRI/DDR333 (PC1600, PC2100, PC2700)
Switching Characteristics - DDRI-400 (PC3200)
SYMBOL
SYMBOL
SYMBOL
t
f
f
f
PDSS
clock
t
t
t
t
t
t
T
max
max
t
PD
phl
PD
PD
phl
SL
S
h
Clock frequency
Output slew rate
Setup time, fast slew rate
Setup time, slow slew rate
Hold time, fast slew rate
Hold time, slow slew rate
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of ≥ 1V/ns.
3 - For data signal input slew rate of ≥ 0.5V/ns and < 1V/ns.
4 - CLK, CLK# signals input slew rate of ≥ 1V/ns.
CLK, CLK# (TSSOP)
CLK, CLK# (VFQFN[MLF2])
RESET#
(VFQFN[MLF2])
CLK, CLK# (TSSOP)
RESET#
PARAMETERS
(Input)
(Input)
From
From
1
2 & 4
3 & 4
2 & 4
3 & 4
Data before CLK↑ , CLK#↓
Data after CLK↑ , CLK#↓
(Output)
(Output)
To
To
Q
Q
Q
Q
Q
Q
Q
7
MIN
MIN
210
210
1.6
1.6
1.1
1.1
V
V
DD
DD
= 2.6V ±0.1V
= 2.5V ±0.2V
TYP
TYP
2.1
2.1
1.6
V
DDQ
MIN
0.4
0.6
0.4
0.5
1
= 2.5V ± 0.2V
MAX
MAX
1.65
1.85
1.9
3.5
2.6
2.6
3.5
MAX
270
4
UNITS
UNITS
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
UNITS
MHz
V/ns
ns
ns
ns
ns
ICSSSTVA16859B
TSD