SSTVA16859BKLF IDT, Integrated Device Technology Inc, SSTVA16859BKLF Datasheet - Page 2

• Manufacturer Part Number: SSTVA16859BKLF
• Description: IC BUFFER DDR 13-26BIT 56VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTVA16859BKLF

• Logic Type: 13-Bit to 26-Bit Registered Buffer, DDR
• Supply Voltage: 2.3 V ~ 2.7 V
• Number Of Bits: 13, 26
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VFQFN, 56-VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ / ICS™ DDR 13-Bit to 26-Bit Registered Buffer
ICSSSTVA16859B
DDR 13-Bit to 26-Bit Registered Buffer
General Description
The 13-bit-to-26-bit ICSSSTVA16859B is a universal bus driver designed for 2.3V to 2.7V V
I/O levels, except for the LVCMOS RESET# input.
Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive
edge of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#,
an LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTVA16859B supports low-
power standby operation. A logic level “Low” at RESET# assures that all internal registers and outputs (Q) are reset
to the logic “Low” state, and all input receivers, data (D) and clock (CLK/CLK#) are switched off. Please note that
RESET# must always be supported with LVCMOS levels at a valid logic state because VREF may not be stable during
power-up.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be held
at a logic “Low” level during power up.
In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and CLK#.
Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state,
the register will be cleared and the outputs will be driven to a logic “Low” level quickly relative to the time to disable
the differential input receivers. This ensures there are no glitches on the output. However, when coming out of low-power
standby state, the register will become active quickly relative to the time to enable the differential input receivers. When
the data inputs are at a logic level “Low” and the clock is stable during the “Low”-to-”High” transition of RESET# until
the input receivers are fully enabled, the design ensures that the outputs will remain at a logic “Low” level.
Pin Configuration (64-Pin TSSOP)
Pin Configuration (56-Pin MLF2)
1050A—01/07/05
- 1
3
, 7
- 1
2
, 6
, 9
, 5
, 5
, 4
, 8
1
1
1
3
8
, 5
2
, 8
, 7
, 6
1 -
1
, 5
0
2
, 4
2
2
P
4
P
1 -
, 6
2
, 7
, 3
0
N I
N I
5
3
8
2
1
, 6
4 -
3
3 -
, 6
3
, 7
, 7
2
, 6
5
3
, 4
N
N
, 3
, 2
, 7
1
, 8
, 7
, 1
6
4
4
4
4
3
3
3
3
3
1
8
U
5
U
-
3
, 7
3
4
, 1
8
9
, 6
5
2 -
3
5
6
, 3
8
2
1
M
M
6
4
3
, 9
, 8
, 4
, 4
3
8
9
, 2
B
6
6
B
4
1
4 -
4
9
4
5
2
0
4
5
E
E
5
, 3
, 7
, 2
, 4
, 3
2 -
R
R
0
5 -
, 5
5
5
5
4
4
, 0
, 9
, 3
, 9
, 6
, 4
2
8
5
6
5
5
4
5
3 -
, 4
4
- 5
5
7
6
2
C
P
P
R
R
e
Q
Q
N I
D
N I
D
V
V
V
V
t n
C
E
C
E
G
G
V
V
C
C
1 (
D
1 (
1 (
D
1 (
R
R
L
S
L
S
N
N
r e
D
D
N
N
L
L
D
D
K
E
K
E
: 3
: 3
E
: 3
: 3
E
A
A
K
D
K
D
D
D
Q
#
Q
#
P
F
F
T
T
) 1
) 1
M
) 1
M
) 1
A
#
#
E
E
D
O
O
I
I
I
I
N I
N I
N I
N I
N I
N I
T
U
N
N
T
U
N
N
P
P
P
P
P
P
P
Y
Y
T
T
W
W
P
P
P
W
P
P
W
W
P
P
P
W
P
P
W
P
P
P
P
U
U
U
U
U
U
U
U
U
U
R
R
R
R
R
R
R
E
E
U
U
T
T
T
T
T
T
T
T
T
T
T
T
2
D
G
O
D
P
N
C
R
n I
D
G
O
D
P
N
C
R
n I
G
o
o
a
a
e
e
a
a
e
e
o
o
o r
u
p
o r
u
p
o r
s
s
s
a t
a t
g
e r
s
a t
a t
g
e r
p t
t u
p t
t u
i t i
i t i
u
u
u
t e
t e
a
a
t u
t u
n
n
n
o
n i
e v
i t
o
n i
e v
i t
s
e r
s
e r
d
d
d
e v
e v
a (
a (
u
u
u
u
p
p
s
s
e f
e f
p t
p
p t
p
(
t u
m
t u
m
i t c
i t c
u
u
M
p
p
m
e r
m
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t u
t u
p
p
a
a
y l
y l
e v
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L
p
p
t s
a
n
t s
a
n
F
y l
y l
t s
c
t s
c
v
v
r e
r e
2
o l
o l
l o
e
l o
e
r e
r e
v
v
p
w
a t
w
l o
a t
v
l o
v
c
c
D
D
a
l o
l o
o l
c
)
o l
c
)
a t
g
a t
g
E
E
k c
o l
o l
a t
a t
k c
, e
k c
, e
S
S
g
g
k c
k c
a
g
g
, e
C
, e
C
2
2
g
n i
n i
, e
, e
R
R
5 .
5 .
e
n i
n i
2
2
p
p
P I
P I
2
2
5 .
V
5 .
V
p
p
o
t u
t u
5 .
5 .
t u
l n
t u
I T
I T
V
V
n
n
V
V
) y
o
o
O
O
n
n
m
m
n
n
o
o
DD
N
N
o
o
m
n i
m
n i
m
m
l a
l a
n i
n i
operation and SSTL_2
n i
n i
l a
l a
l a
l a
ICSSSTVA16859B
TSD