SSTUA32864BHLF IDT, Integrated Device Technology Inc, SSTUA32864BHLF Datasheet - Page 2

• Manufacturer Part Number: SSTUA32864BHLF
• Description: IC REGIST BUFFER 25BIT DDR 96BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTUA32864BHLF

• Logic Type: 1:1, 1:2 Configurable Registered Buffer
• Supply Voltage: 1.8V
• Number Of Bits: 25, 14
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 96-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General Description
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All
outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. ICSSSTUA32864B operates
from a differential clock (CK and CK#). Data are registered at the crossing of CK going high, and CK# going low.
The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when low) to B configuration (when
high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high).
The device supports low-power standby operation. When the reset input (RST#) is low, the differential input receivers
are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when
RST# is low all registers are reset, and all outputs are forced low. The LVCMOS RST# and Cn inputs must always be
held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied,
RST# must be held in the low state during power up.
In the DDR-II RDIMM application, RST# is specified to be completely asynchronous with respect to CK and CK#.
Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared
and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers.
As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RST# until
the input receivers are fully enabled, the design of the ICSSSTUA32864B must ensure that the outputs will remain
low, thus ensuring no glitches on the output.
The device monitors both DCS# and CSR# inputs and will gate the Qn outputs from changing states when both DCS#
and CSR# inputs are high. If either DCS# or CSR# input is low, the Qn outputs will function normally. The RST input
has priority over the DCS# and CSR# control and will force the outputs low. If the DCS#-control functionality is not
desired, then the CSR# input can be hardwired to ground, in which case, the setup-time requirement for DCS# would
be the same as for the other D data inputs. Package options include 96-ball LFBGA (MO-205CC).
1055A—01/28/05
M
A
B
C
D
G
H
K
N
R
E
F
L
P
T
J
1:2 Register A (C0 = 0, C1 = 1)
DCKE
D2
D3
DODT
D5
D6
NC
CK
CK#
D8
D9
D10
D11
D12
D13
D14
1
Ball Assignments
NC
NC
NC
NC
NC
NC
RST#
DCS#
CSR#
NC
NC
NC
NC
NC
NC
NC
2
V
GND
V
GND
V
GND
V
GND
V
GND
V
GND
V
GND
V
V
REF
DD
DD
DD
DD
DD
DD
DD
REF
3
V
GND
V
GND
V
GND
V
GND
V
GND
V
GND
V
GND
V
V
DD
DD
DD
DD
DD
DD
DD
DD
DD
4
QCKEA
Q2A
Q3A
QODTA
Q5A
Q6A
C1
QCSA#
ZOH
Q8A
Q9A
Q10A
Q11A
Q12A
Q13A
Q14A
5
QCKEB
Q2B
Q3B
QODTB
Q5B
Q6B
C0
ZOL
Q8B
Q9B
Q10B
Q11B
Q12B
Q13B
Q14B
QCSB#
6
2
M
A
D
G
H
K
N
B
C
E
F
L
P
R
T
J
1:2 Register B (C0 = 1, C1 = 1)
D1
D2
D3
D4
D5
D6
NC
CK
CK#
D8
D9
D10
DODT
D12
D13
DCKE
1
Ball Assignments
NC
NC
NC
NC
NC
NC
RST#
DCS#
CSR#
NC
NC
NC
NC
NC
NC
NC
2
ICSSSTUA32864B
V
GND
V
GND
V
GND
V
GND
V
GND
V
GND
V
GND
V
V
REF
DD
DD
DD
DD
DD
DD
DD
REF
3
V
GND
V
GND
V
GND
V
GND
V
GND
V
GND
V
GND
V
V
DD
DD
DD
DD
DD
DD
DD
DD
DD
4
Q1A
Q2A
Q3A
Q4A
Q5A
Q6A
C1
QCSA#
ZOH
Q8A
Q9A
Q10A
QODTA
Q12A
Q13A
QCKEA
5
Q1B
Q2B
Q3B
Q4B
Q5B
Q6B
C0
ZOL
Q8B
Q9B
Q10B
QODTB
Q12B
Q13B
QCKEB
QCSB#
6