GTL2005PW,118 NXP Semiconductors, GTL2005PW,118 Datasheet

IC XLATR QUAD BI-DIREC 14-TSSOP

GTL2005PW,118

Manufacturer Part Number
GTL2005PW,118
Description
IC XLATR QUAD BI-DIREC 14-TSSOP
Manufacturer
NXP Semiconductors
Datasheet

Specifications of GTL2005PW,118

Package / Case
14-TSSOP
Logic Function
Translator, Bidirectional
Number Of Bits
4
Input Type
GTL
Output Type
LVTTL, TTL
Number Of Channels
4
Number Of Outputs/channel
1
Differential - Input:output
No/No
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Supply Voltage
3 V ~ 3.6 V
Logic Type
Translator
Logic Family
GTL
Translation
GTL/GTL+ to LVTTL/TTL
Input Bias Current (max)
3 mA
High Level Output Current
- 12 mA
Low Level Output Current
40 mA
Propagation Delay Time
4.4 ns (Typ) @ 3.3 V
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Rate
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-1000-2
935263813118
GTL2005PW-T

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
GTL2005PW,118
Manufacturer:
NXP/恩智浦
Quantity:
20 000
1. General description
2. Features
The GTL2005 is a quad translating transceiver designed for 3.3 V system interface with a
GTL/GTL+ bus.
The direction pin (DIR) allows the part to function as either a GTL-to-TTL sampling
receiver or as a TTL-to-GTL interface.
The GTL2005 LVTTL interface is tolerant up to 5.5 V allowing direct access to TTL or 5 V
CMOS outputs.
The GTL2005 V
allows, use the GTL2014, otherwise more closely review noise margins.
I
I
I
I
I
I
I
Fig 1.
GTL2005
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched
translator
Rev. 07 — 3 February 2009
Operates as a quad GTL/GTL+ sampling receiver or as a LVTTL/TTL to GTL/GTL+
driver
Quad bidirectional bus interface
3.0 V to 3.6 V operation with 5 V tolerant LVTTL I/O
Live insertion/extraction permitted
Latch-up protection exceeds 500 mA per JESD78
ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per
JESD22-A115, and 1000 V CDM per JESD22-CC101
Package offered: TSSOP14
GTL2005/GTL2014 positioning
ref
linearity degrades below 0.8 V (see
slow t
fast t
PD
PD
GTL
GTL2014
GTL
GTL2005
Section
GTL
002aab378
10.1). If the application
Product data sheet

Related parts for GTL2005PW,118

GTL2005PW,118 Summary of contents

Page 1

GTL2005 Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator Rev. 07 — 3 February 2009 1. General description The GTL2005 is a quad translating transceiver designed for 3.3 V system interface with a GTL/GTL+ bus. The direction pin (DIR) allows the ...

Page 2

... NXP Semiconductors 3. Quick reference data Table 3 Symbol GTL PLH t PHL t PLH t PHL [1] All typical values are measured Ordering information Table +85 C amb Type number GTL2005PW GTL2005_7 Product data sheet Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator Quick reference data 0.3 V Parameter input capacitance input/output capacitance = 0 ...

Page 3

... NXP Semiconductors 5. Functional diagram Fig 2. 6. Pinning information 6.1 Pinning Fig 3. GTL2005_7 Product data sheet Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator GTL2005 VREF Logic diagram of GTL2005 DIR GTL2005PW VREF GND Pin configuration for TSSOP14 Rev. 07 — 3 February 2009 GTL2005 B0 B1 ...

Page 4

... NXP Semiconductors 6.2 Pin description Table 3. Symbol DIR VREF GND Functional description Refer to 7.1 Function table Table HIGH voltage level LOW voltage level. Input DIR H L GTL2005_7 Product data sheet Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator Pin description Pin Description 1 direction control input ...

Page 5

... NXP Semiconductors 8. Limiting values Table 5. In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol stg [1] Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Section 9 “ ...

Page 6

... NXP Semiconductors 9. Recommended operating conditions Table 6. Symbol Parameter ref amb [1] Unused inputs must be held HIGH or LOW to prevent them from floating. [2] V ref within this range and does not need to follow GTL-/GTL/GTL+ specification. [3] Nominally 50 mV around GTL2005_7 Product data sheet ...

Page 7

... NXP Semiconductors 10. Static characteristics Table 7. Static characteristics Recommended operating conditions; voltages are referenced to GND (ground = 0 V); T Symbol Parameter V HIGH-level output OH voltage V LOW-level output OL voltage I input current I I output OFF current OFF I high contention over EX voltage leakage current I supply current CC [3] I additional supply ...

Page 8

... NXP Semiconductors 10.1 Performance curves 1200 V TH and V TH (mV) 1000 800 V ref 600 400 0.5 0.6 0 (mV 3 Fig 4. GTL V and V versus V TH+ TH GTL2005_7 Product data sheet Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator 002aab152 V TH and V TH (mV 0.9 1.0 V (V) ...

Page 9

... NXP Semiconductors 1200 V TH and V TH (mV) 1000 V ref 800 600 400 0.5 0.6 0 (mV 3 Fig 5. GTL V and V versus V TH+ TH GTL2005_7 Product data sheet Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator 002aab155 V TH and V TH (mV 0.9 1.0 V (V) ref 1200 TH and ...

Page 10

... NXP Semiconductors 1200 V TH and V TH (mV) 1000 V TH 800 600 V ref 400 0.5 0.6 0 (mV 3 Fig 6. GTL V and V versus V TH+ TH GTL2005_7 Product data sheet Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator 002aab158 V TH and V TH (mV 0.9 1.0 V (V) ref 1200 ...

Page 11

... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics V = 3 Symbol Parameter GTL ; V = 0.6 V ref t propagation delay PLH t PHL t propagation delay PLH t PHL GTL 0.8 V ref t propagation delay PLH t PHL t propagation delay PLH t PHL GTL 1.0 V ref t propagation delay PLH t PHL t propagation delay ...

Page 12

... NXP Semiconductors Fig 8. 12. Test information Fig 9. Fig 10. Load circuit for A (GTL) outputs R — Load resistor L C — Load capacitance; includes jig and probe capacitance L R — Termination resistance; should be equal GTL2005_7 Product data sheet Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator ...

Page 13

... NXP Semiconductors 13. Package outline TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...

Page 14

... NXP Semiconductors 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

Page 15

... NXP Semiconductors 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...

Page 16

... NXP Semiconductors Fig 12. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 15. Abbreviations Table 11. Acronym CDM CMOS DUT ESD GTL HBM I/O LVTTL MM TTL GTL2005_7 Product data sheet ...

Page 17

... NXP Semiconductors 16. Revision history Table 12. Revision history Document ID Release date GTL2005_7 20090203 • Modifications: Figure 2 “Logic diagram of GTL2005” reversed • updated soldering information GTL2005_6 20070906 GTL2005_5 20050406 (9397 750 14285) GTL2005_4 20040510 (9397 750 13104) GTL2005_3 20000619 (9397 750 07222) ...

Page 18

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 19

... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 4 7.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics 10.1 Performance curves . . . . . . . . . . . . . . . . . . . . . 8 11 Dynamic characteristics ...

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