MC100LVELT22DG ON Semiconductor, MC100LVELT22DG Datasheet

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MC100LVELT22DG

Manufacturer Part Number
MC100LVELT22DG
Description
IC TRANSLATOR DUAL 3.3V 8SOIC
Manufacturer
ON Semiconductor
Series
100LVELTr
Datasheet

Specifications of MC100LVELT22DG

Logic Function
Translator
Number Of Bits
2
Input Type
LVCMOS, LVTTL
Output Type
LVPECL
Number Of Channels
2
Number Of Outputs/channel
1
Differential - Input:output
No/Yes
Propagation Delay (max)
0.6ns
Voltage - Supply
3 V ~ 3.8 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Supply Voltage
3 V ~ 3.8 V
Logic Type
Translator
Logic Family
ECL
Translation
LVCMOS/LVTTL to LVPECL
Propagation Delay Time
0.6 ns
Supply Voltage (max)
3.8 V
Supply Voltage (min)
3 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Rate
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
MC100LVELT22DGOS

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MC100LVELT22DG
Manufacturer:
ON Semiconductor
Quantity:
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Part Number:
MC100LVELT22DG
Manufacturer:
ON/安森美
Quantity:
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MC100LVELT22
3.3V Dual LVTTL/LVCMOS
to Differential LVPECL
Translator
Description
LVPECL translator. Because LVPECL (Low Voltage Positive ECL)
levels are used, only +3.3 V and ground are required. The small outline
8-lead package and the low skew, dual gate design of the LVELT22
makes it ideal for applications which require the translation of a clock
and a data signal.
Features
© Semiconductor Components Industries, LLC, 2008
August, 2008 − Rev. 8
The MC100LVELT22 is a dual LVTTL/LVCMOS to differential
with GND = 0 V
350 ps Typical Propagation Delay
<100 ps Output−to−Output Skew
Flow Through Pinouts
The 100 Series Contains Temperature Compensation
LVPECL Operating Range: V
When Unused TTL Input is left Open, Q Output will Default High
Pb−Free Packages are Available
CC
= 3.0 V to 3.8 V
1
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
CASE 506AA
CASE 948R
MN SUFFIX
*For additional marking information, refer to
DT SUFFIX
CASE 751
D SUFFIX
TSSOP−8
8
Application Note AND8002/D.
(Note: Microdot may be in either location)
SOIC−8
8
DFN8
ORDERING INFORMATION
1
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb−Free Package
http://onsemi.com
Publication Order Number:
DIAGRAMS*
MC100LVELT22/D
8
1
MARKING
8
1
ALYWG
1
KVT22
ALYW
KR22
G
G
4

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MC100LVELT22DG Summary of contents

Page 1

MC100LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator Description The MC100LVELT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL (Low Voltage Positive ECL) levels are used, only +3.3 V and ground are required. The small outline 8-lead package and ...

Page 2

LVTTL/ LVPECL LVCMOS Figure 1. 8−Lead Pinout (Top View) and Logic Diagram EP Table 2. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of ...

Page 3

Table 4. LVPECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current CC V Output HIGH Voltage (Note Output LOW Voltage (Note 4) OL NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted ...

Page 4

... Q Driver Device Q Figure 1. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100LVELT22D MC100LVELT22DG MC100LVELT22DR2 MC100LVELT22DR2G MC100LVELT22DT MC100LVELT22DTG MC100LVELT22DTR2 MC100LVELT22DTR2G MC100LVELT22MNR4 MC100LVELT22MNRG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D ...

Page 5

... G C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004 SOLDERING FOOTPRINT* 1 ...

Page 6

K 8x REF 0.10 (0.004) 0.15 (0.006 L −U− PIN 1 IDENT 0.15 (0.006 −V− C 0.10 (0.004) D −T− G SEATING PLANE PACKAGE DIMENSIONS TSSOP−8 ...

Page 7

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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