M95256-DFDW6TP STMicroelectronics, M95256-DFDW6TP Datasheet - Page 25

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M95256-DFDW6TP

Manufacturer Part Number
M95256-DFDW6TP
Description
EEPROM 256-Kbit serial SPI bus EEPROM
Manufacturer
STMicroelectronics
Datasheet

Specifications of M95256-DFDW6TP

Rohs
yes
Memory Size
256 Kbit
Organization
32768 x 8 bit
Data Retention
200 yr
Maximum Clock Frequency
20 MHz
Maximum Operating Current
5 mA
Operating Supply Voltage
1.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-8
Interface Type
SPI
Minimum Operating Temperature
- 40 C
Supply Voltage - Max
5.5 V
Supply Voltage - Min
1.7 V

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M95256-W M95256-R M95256-DR M95256-DF
6.6.1
Cycling with Error Correction Code (ECC)
M95256 and M95256-D devices offer an Error Correction Code (ECC) logic. The ECC is an
internal logic function which is transparent for the SPI communication protocol.
The ECC logic is implemented on each group of four EEPROM bytes
single bit out of the four bytes happens to be erroneous during a Read operation, the ECC
detects this bit and replaces it with the correct value. The read reliability is therefore much
improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be
written/cycled independently. In this case, the ECC function also writes/cycles the three
other bytes located in the same group
defined at group level and the cycling can be distributed over the four bytes of the group: the
sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain
below the maximum value defined in
c. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.
Doc ID 12276 Rev 19
Table
(c)
. As a consequence, the maximum cycling budget is
14.
(c)
. Inside a group, if a
Instructions
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