ATAES132-SH-EQ Atmel, ATAES132-SH-EQ Datasheet - Page 10

• Manufacturer Part Number: ATAES132-SH-EQ
• Description: EEPROM AES 32Kbit EE SPI
• Manufacturer: Atmel

Specifications of ATAES132-SH-EQ

• Rohs: yes
• Maximum Clock Frequency: 10 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: SPI
• Factory Pack Quantity: 2300

2.3.1.
2.4.
2.4.1.
2.4.2.
2.4.3.
2.4.4.
Non-reversible Monotonic Counters
The ATAES132 includes 16 monotonic nonvolatile (EEPROM) counters which can only be incremented. They can never be
decremented or reset and are protected even if the power is interrupted during an increment operation. These monotonic
counters can be used to track system usage or to store small values. Keys can also be configured to prevent exhaustive
attacks by limiting key usage with a counter. Each counter has an associated counter configuration register in the configuration
memory.
Each counter can increment up to a value of 2,097,134 using the count command; after which they can be no longer changed.
Counters attached to keys are incremented each time the key is used – when the usage counter reaches its limit the key is
disabled.
On shipment from Atmel, the EEPROM locations are initialized to their lowest value. The initial value of each counter may be
written to a different value prior at personalization prior to locking the configuration. See Appendix H for additional information.
SRAM Memory
The ATAES132 SRAM is used to store volatile data and status information. The ATAES132 SRAM buffers and registers are
mapped into the top of the memory address space, and are accessed using standard EEPROM read/write commands. The
command memory buffer is used to send extended commands to the device. The response memory buffer is used to read
responses to the extended commands from the device. An IO address reset register is used to reset the buffer address
pointers. The STATUS register reports the state of the device.
The VolatileKey register and the authentication status register are stored in the SRAM and are managed by the internal logic.
These registers can not be directly written or read by the user.
Nonce
The SRAM is used to store the nonce and the random number generator (RNG) seed. The RNG seed is generated
automatically by the ATAES132 as described in Section 3.6. The nonce is generated using the nonce command or the
NonceCompute command. The nonce and RNG seed register are erased when the device loses power, enters the sleep state,
or is reset.
VolatileKey
The SRAM contains a session key register named VolatileKey. This key location can be written with the KeyCompute,
KeyImport, KeyLoad, or KeyTransfer commands. The VolatileKey register is erased when the device loses power, enters the
sleep state, or is reset. Restrictions on the VolatileKey are established when the register is created/loaded and persist until
the power is lost or the key is reloaded.
The VolatileKey can never be used to read or write the user memory or to authenticate increments of the monotonic counters.
VolatileKey can only be used to perform authentication operations and to encrypt or decrypt external data. See Section 4.3
for the VolatileKey usage restrictions.
Command Memory Buffer
The host executes extended the ATAES132 commands by writing a command block to the command memory buffer using a
standard SPI or I
the integrity of the block by checking the 16-bit checksum, and then executes the requested operation.
Response Memory Buffer
The host receives responses to the extended ATAES132 commands by reading a response block from the response memory
buffer using a standard SPI or I
the response packet after an ATAES132 command is processed.
2
C write command. After the host completes its write operation to the SRAM buffer, the ATAES132 verifies
2
C read command. The base address of the response memory buffer contains the first byte of
Atmel ATAES132 Preliminary Datasheet
8760A−CRYPTO−5/11
10