M95128-DFMC6TG STMicroelectronics, M95128-DFMC6TG Datasheet - Page 20

• Manufacturer Part Number: M95128-DFMC6TG
• Description: EEPROM 128Kbit SPI EE 20 MHz 1.8 to 5.5
• Manufacturer: STMicroelectronics

Specifications of M95128-DFMC6TG

• Rohs: yes

Instructions
6.4
20/49
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction is used to write new values to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must have been
previously executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,
followed by the instruction code, the data byte on Serial Data input (D) and Chip Select (S)
driven high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that
latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).
Otherwise, the Write Status Register (WRSR) instruction is not executed.
The instruction sequence is shown in
Figure 11. Write Status Register (WRSR) sequence
Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self-
timed Write cycle that takes t
and AC
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed
Write cycle t
also reset at the end of the Write cycle t
The Write Status Register (WRSR) instruction enables the user to change the values of the
BP1, BP0 and SRWD bits:
●
●
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the t
The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in
the Status Register. Bits b6, b5, b4 are always read as 0.
The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as
read-only, as defined in
The SRWD (Status Register Write Disable) bit, in accordance with the signal read on
the Write Protect pin (W), enables the user to set or reset the Write protection mode of
the Status Register itself, as defined in
Write Status Register (WRSR) instruction is not executed.
parameters).
S
C
D
Q
W
, and 0 when the Write cycle is complete. The WEL bit (Write Enable Latch) is
0
1
High Impedance
Table
W
Doc ID 5798 Rev 16
2
to complete (as specified in AC tables under
Instruction
W
3
2.
Write cycle.
4
Figure
5
W
.
6
Table
11.
7
MSB
7
8
7. When in Write-protected mode, the
6
9 10 11 12 13 14 15
5
Register In
4
M95128-W M95128-R M95128-DF
Status
3
2
1
0
AI02282D
Section 9: DC