ATAES132-TH-EQ-T Atmel, ATAES132-TH-EQ-T Datasheet - Page 101

• Manufacturer Part Number: ATAES132-TH-EQ-T
• Description: EEPROM AES 32Kbit EE SPI
• Manufacturer: Atmel

Specifications of ATAES132-TH-EQ-T

• Rohs: yes
• Maximum Clock Frequency: 10 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-8
• Interface Type: SPI
• Factory Pack Quantity: 4000

G.2.8. Read Response Memory Buffer
G.2.9. Write IO Address Reset Register
Table G-29. After an I
Writing the command memory buffer resets the response memory buffer pointer to the base address. Writing the command
memory buffer does not change the response memory buffer contents until the entire command block is received and
processed.
The host can re-write the contents of the command memory buffer by resetting the buffer pointer (by writing the IO address
reset register) and sending a write memory instruction (BWRITE, PWRITE) with a starting address of 0xFE00.
Note:
To read the Response Memory Buffer the host sends a Random Read memory instruction (RREAD) with a starting address of
0xFE00 when ATAES132 ACKs the I
Buffer without causing an error. As each byte is read, the Response Memory Buffer pointer increments by 1. If the host reads
beyond the end of the Response Block, then 0xFF will be returned for any byte after the Checksum.
Reading the Response Memory Buffer does not change the Command Memory Buffer contents or the Response Memory
Buffer contents. Reading the Response Memory Buffer resets the Command Memory Buffer pointer to the base address.
Reading the Response Memory Buffer does not change the STATUS register.
The host can re-read the contents of the Response Memory Buffer by resetting the buffer pointer (by writing the IO Address
Reset register) and sending a Random Read memory instruction (RREAD) with a starting address of 0xFE00.
To reset the pointer for the command memory buffer and the pointer for the response memory buffer, the host sends a write
memory instruction (BWRITE, or PWRITE) with a starting address of 0xFFE0. The IO address reset register can be written
with 1 to 32 bytes of data without generating an error – the data bytes will be ignored. The command and the response
memory buffer pointers are set to the base address of the buffers. The command memory buffer is empty, and the response
memory buffer contents are unchanged. Writing the IO address reset register changes the CRCE status bit to 0b – all of the
other STATUS bits are unchanged.
Bit
Bit 0 (WIP)
Bit 1 (WEN)
Bit 2 (WAKEb)
Bit 3 (Reserved)
Bit 4 (CRCE)
Bit 5 (Reserved)
Bit 6 (RRDY)
Bit 7 (EERR)
If the host must write the command memory buffer with more bytes than is required to send the command block
due to hardware limitations, then the host should transmit 0xFF bytes after the checksum. The extra bytes will be
discarded by the ATAES132 and will not result in a buffer overrun, or any other error.
2
C write command memory buffer resulting in CRCE = 0b , the STATUS register contains:
Definition
“0b” indicates the device is ready, waiting for a command
"0b" indicates the device is in I
"0b" indicates the device is not in the sleep or standby power state
Always "0b"
"0b" indicates no checksum error
Always "0b"
"1b" indicates the response memory buffer contains a response block
"0b" indicates no errors during execution of the command block
"1b" indicates the command block generated an error; see the ReturnCode for the cause
2
C device address. The host can read any number of bytes from the Response Memory
2
C interface mode
Atmel ATAES132 Preliminary Datasheet
8760A−CRYPTO−5/11
101