ATAES132-MA3H-EQ-T Atmel, ATAES132-MA3H-EQ-T Datasheet - Page 99

• Manufacturer Part Number: ATAES132-MA3H-EQ-T
• Description: EEPROM AES 32Kbit (MA3) SPI
• Manufacturer: Atmel

Specifications of ATAES132-MA3H-EQ-T

• Rohs: yes
• Maximum Clock Frequency: 10 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: UDFN-8
• Interface Type: SPI
• Factory Pack Quantity: 5000

G.2.6. Write User Memory
Table G-25. After an I
Note:
The ATAES132 instructions for directly writing the user memory are identical to the standard Atmel Serial EEPROM. The host
can send a write memory instruction (BWRITE, PWRITE) whenever the ATAES132 ACKs the I
address being written is valid, access requirements have been satisfied, and no page boundaries are crossed, then the data
provided by the host will be written after the host generates an I
prohibited for any reason, then the ATAES132 will discard the data and no EEPROM write will occur.
A memory write operation begins with an I
not provide an I
indicate the ATAES132 is waiting for a command.
If the host provides the required I
write operation. When the write operation is complete, then ATAES132 will ACK the I
Upon completion of a memory write operation, the command memory buffer is empty, and the response memory buffer
contains a ReturnCode. The command and the response memory buffer pointers are set to the base address of the buffers.
The STATUS will be as shown in Table G-5.
Table G-26. After an I
Bit
Bit 0 (WIP)
Bit 1 (WEN)
Bit 2 (WAKEb)
Bit 3 (Reserved)
Bit 4 (CRCE)
Bit 5 (Reserved)
Bit 6 (RRDY)
Bit 7 (EERR)
Bit
Bit 0 (WIP)
Bit 1 (WEN)
Bit 2 (WAKEb)
Bit 3 (Reserved)
Bit 4 (CRCE)
Bit 5 (Reserved)
Bit 6 (RRDY)
Bit 7 (EERR)
1.
A read memory operation does not change the contents of the response memory buffer. The EERR status bit is
used to indicate success, or to indicate an error. No ReturnCode is generated by a memory read error.
2
C stop condition, then no write will occur, no ReturnCode will be generated, and the STATUS is 0x00 to
2
2
C read memory operation, the STATUS register contains:
C write memory operation, the STATUS register contains:
Definition
“0b” indicates the device is ready, waiting for a command
"0b" indicates the device is in I
"0b" indicates the device is not in the sleep or standby power state
Always "0b"
"0b" indicates no checksum error
Always "0b"
"0b" indicates the response memory buffer is unchanged
"0b" indicates no errors during execution of the read operation
"1b" indicates 0xFF was returned in place of one or more invalid or prohibited bytes read
Definition
“0b” indicates the device is ready, waiting for a command
"0b" indicates the device is in I
"0b" indicates the device is not in the sleep or standby power state
Always "0b"
"0b" indicates no checksum error
Always "0b"
"1b" indicates the response memory buffer contains a response block
"0b" indicates no errors during execution of the write operation
"1b" indicates the write operation generated an error; see the ReturnCode for the cause
2
C stop condition, then the ATAES132 will NAK the I
2
C start condition and ends with a I
2
2
C interface mode
C interface mode
2
C stop condition. If the address is invalid, or access is
Atmel ATAES132 Preliminary Datasheet
2
C stop condition by the host. If the host does
(1)
2
2
C device address during the EEPROM
C device address.
2
C device address. If the
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