ATAES132-SH-ER-T Atmel, ATAES132-SH-ER-T Datasheet - Page 156

• Manufacturer Part Number: ATAES132-SH-ER-T
• Description: EEPROM AES 32Kbit EE I2C
• Manufacturer: Atmel

Specifications of ATAES132-SH-ER-T

• Rohs: yes
• Maximum Clock Frequency: 1 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: I2C
• Factory Pack Quantity: 4000

P.2.8. Write Status Register Command (WRSR)
P.2.9. Block Write Protect
P.2.10. Standby Mode
P.2.11. Operating Voltage
P.2.12. Maximum Operating Frequency
The ATAES132 STATUS register definition is shown in Table P-2 and described in Appendix G. The default state of all
STATUS bits is 0b. The WEN, WIP, and reserved bits are similar to standard SPI Serial EEPROM: If WEN = 1b, then the
device is write enabled. If WIP = 0b, the device is ready to accept a command; WIP = 1b indicates a write cycle or a
cryptographic operation is in progress. The reserved bits are 0b except when an internal write cycle or a cryptographic
operation is in progress. All bits of the STATUS register are 1b when an internal write cycle or a cryptographic operation is in
progress.
Table P-50. Atmel ATAES132 STATUS register definition
ATAES132 reports errors to the host using the EERR and CRCE bits. The RRDY bit indicates if the Response Memory Buffer
is empty (0b), or ready to read (1b). The WAKEb bit indicates if the device is in the Sleep or Standby Power State. See
Section G.1 for detailed descriptions of each STATUS bit.
The AT25320B STATUS register contains three bits which control the block write protect function, and the write protect pin.
These bits can be changed by sending a write status register (WRSR) command to the memory.
The ATAES132 does not support the write status register (WRSR) command. The WRSR command will be ignored if it is
received.
The AT25320B STATUS register contains two block protect bits (BP0 and BP1) which control the block write protect function.
By writing the STATUS register the user can set the block protect bits to inhibit writes in ¼, ½, or the full memory array.
On the ATAES132, the user memory write permissions are controlled by the ZoneConfig Registers (see Section E.2.22). The
user memory is divided into 16 user zones which are independently controlled by 16 ZoneConfig Registers – different write
permissions can be assigned to different sections of the memory. By default all user memory has open write access.
Standard SPI EEPROM automatically enter low power standby mode upon completion of any internal operation.
The ATAES132 has three powered states: the active state and two low power states, the standby state and the sleep state.
The ATAES132 will remain in the active state between operations unless the host sends a sleep command to activate the
standby state or the sleep state. The ATAES132 can also be configured to automatically enter a low power state at power up.
See Appendix L for details on the power management features.
The AT25320B operating voltage range is 1.8V minimum to 5.5V maximum.
The ATAES132 operating voltage range is 2.5V minimum to 5.5V maximum. See Section 9.3 for DC specifications.
The AT25320B maximum SCK frequency is 10MHz when V
V
The ATAES132 maximum SCK frequency is 10MHz when V
CC
EERR
is 4.5 V to 5.5 V.
Bit 7
RRDY
Bit 6
Reserved
Bit 5
CRCE
Bit 4
CC
CC
is 2.7 V to 5.5 V. The maximum SCK frequency is 20MHz when
is 2.5 V to 5.5 V. See Section 9.4 for AC specifications.
Reserved
Bit 3
Atmel ATAES132 Preliminary Datasheet
WAKEb
Bit 2
WEN
Bit 1
8760A−CRYPTO−5/11
Bit 0
WIP
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