OR2T26A6S208-DB Lattice, OR2T26A6S208-DB Datasheet

OR2T26A6S208-DB

Manufacturer Part Number

OR2T26A6S208-DB

Description

FPGA - Field Programmable Gate Array Use LatticeEC

Manufacturer

Lattice

Datasheet

1.OR2T26A6S208I-DB.pdf (6 pages)

Specifications of OR2T26A6S208-DB

Number Of Gates

63 K

Number Of I/os

384

Maximum Operating Frequency

40 MHz

Operating Supply Voltage

3.3 V

Maximum Operating Temperature

+ 70 C

Mounting Style

SMD/SMT

Package / Case

2T26A-208

Minimum Operating Temperature

0 C

Factory Pack Quantity

120

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

OR2T26A6S208-DB

Manufacturer:

Lattice Semiconductor Corporation

Quantity:

10 000

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Product Brief

December 2005

Features

■

Table 1 . ORCA Series 2 FPGAs

* The ﬁrst number in the usable gates column assumes 48 gates per PFU (12 gates per four-input LUT/FF pair) for logic-only designs. The

OR2C40A/OR2T40A/OR2T40B

second number assumes 30% of a design is RAM. PFUs used as RAM are counted at four gates per bit, with each PFU capable of

implementing a 16 x 4 RAM (or 256 gates) per PFU.

High-performance, cost-effective, low-power

0.35 μm CMOS technology (OR2CxxA), 0.3 μm CMOS

technology (OR2TxxA), and 0.25 μm CMOS technology

(OR2TxxB), (four-input look-up table (LUT) delay less

than 1.0 ns with -8 speed grade)

High density (up to 43,200 usable, logic-only gates; or

99,400 gates including RAM)

Up to 480 user I/Os (OR2TxxA and OR2TxxB I/Os are

5 V tolerant to allow interconnection to both 3.3 V and

5 V devices, selectable on a per-pin basis)

Four 16-bit look-up tables and four latches/ﬂip-ﬂops per

PFU, nibble-oriented for implementing 4-, 8-, 16-, and/or

32-bit (or wider) bus structures

Eight 3-state buffers per PFU for on-chip bus structures

Fast on-chip user SRAM has features to simplify RAM

design and increase RAM speed:

— Asynchronous single port: 64 bits/PFU

— Synchronous single port: 64 bits/PFU

— Synchronous dual port: 32 bits/PFU

Improved ability to combine PFUs to create larger RAM

structures using write-port enable and 3-state buffers

Fast, dense multipliers can be created with the multiplier

mode (4 x 1 multiplier/PFU):

— 8 x 8 multiplier requires only 16 PFUs

— 30% increase in speed

Flip-ﬂop/latch options to allow programmable priority of

synchronous set/reset vs. clock enable

Enhanced cascadable nibble-wide data path

capabilities for adders, subtractors, counters, multipliers,

and comparators including internal fast-carry operation

OR2C04A/OR2T04A

OR2C06A/OR2T06A

OR2C08A/OR2T08A

OR2C10A/OR2T10A

OR2C12A/OR2T12A

OR2C15A/OR2T15B

OR2C26A/OR2T26A

Device

12,300—28,300

15,600—35,800

19,200—44,200

27,600—63,600

43,200—99,400

4,800—11,000

6,900—15,900

9,400—21,600

Usable

Gates*

LUTs

1024

1296

1600

2304

3600

Field-Programmable Gate Arrays

400

576

784

■

* IEEE is a registered trademark of The Institute of Electrical and

Innovative, abundant, and hierarchical nibble-

oriented routing resources that allow automatic use of

internal gates for all device densities without sacriﬁcing

performance

Upward bit stream compatible from the ORCA ATT2Cxx/

ATT2Txx series of devices

Pinout-compatible with new ORCA Series 3 FPGAs

TTL or CMOS input levels programmable per pin for the

OR2CxxA (5 V) devices

Individually programmable drive capability: 12 mA

sink/6 mA source or 6 mA sink/3 mA source

Built-in boundary scan ( IEEE

TS_ALL testability function to 3-state all I/O pins.

Multiple conﬁguration options, including simple, low pin-

count serial ROMs, and peripheral or JTAG modes for in-

system programming (ISP)

Full PCI bus compliance for all devices

Supported by industry-standard CAE tools for design

entry, synthesis, and simulation with ORCA Foundry

Development System support (for back-end implementa-

tion)

New added features (OR2TxxB) provide:

— More I/O per package than the OR2TxxA family.

— No dedicated 5 V supply (VDD5).

— Faster conﬁguration speed (40 MHz).

— Full PCI bus compliance in both 5 V and 3.3 V PCI

Electronics Engineers, Inc.

systems. Pin selectable I/O clamping diodes provide

5 V or 3.3 V PCI compliance and 5 V tolerance.

Registers

1024

1296

1600

2304

3600

400

576

724

Max User

RAM Bits

12,544

16,384

20,736

25,600

36,864

57,600

6,400

9,216

ORCA

†

1149.1 JTAG) and

User

I/Os

160

192

224

256

288

320

384

480

Series 2

Array Size

10 x 10

12 x 12

14 x 14

16 x 16

18 x 18

20 x 20

24 x 24

30 x 30

Related parts for OR2T26A6S208-DB

OR2T26A6S208-DB Summary of contents

Page 1

Product Brief December 2005 Features High-performance, cost-effective, low-power ■ 0.35 μm CMOS technology (OR2CxxA), 0.3 μm CMOS technology (OR2TxxA), and 0.25 μm CMOS technology (OR2TxxB), (four-input look-up table (LUT) delay less than 1.0 ns with -8 speed grade) High density ...

Page 2

... REG3 PFU_NAND D2 A4 WD2 REG2 SR F1 PFU_MUX D1 C REG1 WD1 SR PFU_XOR WD0 REG0 Figure 1. PFU Block Diagram Product Brief December 2005 COUT Lattice Semiconductor 5-4573(F) ...

Page 3

... Product Brief December 2005 Description (continued) A. Simpliﬁed Diagram of OR2CxxA Programmable I/O Cell B. Simpliﬁed Diagram of OR2TxxA/OR2TxxB Programmable I/O Cell Lattice Semiconductor V DD PULL-UP DELAY dintb, dinlr in TTL/CMOS POLARITY PAD TRI DOUT/OUT SLEW RATE POLARITY PULL-DOWN V DD PULL-UP DELAY dintb, dinlr in POLARITY PAD ...

Page 4

... Product Brief December 2005 -6A -7A -7B -8B 129.9 144.9 131.6 149.3 129.9 144.9 131.6 149.3 36.0 40.3 37.7 44.8 107.5 122.0 103.1 120.5 125.0 142.9 123.5 142.9 53.8 62.5 57.5 69.4 92.6 96.2 97.7 112.4 92.6 96.2 97.7 112.4 5.6 5.2 6.1 5.1 4.6 4.3 4.8 4.0 Lattice Semiconductor Unit MHz MHz MHz MHz MHz MHz MHz MHz ns ns ...

Page 5

... OR2C12A, -4 speed grade, 240-pin shrink quad ﬂat pack, commercial temperature. Table 3. FPGA Voltage Options Device OR2CxxA OR2TxxA OR2TxxB Table 4. FPGA Temperature Options Symbol Description (Blank) Commercial I Industrial Lattice Semiconductor OR2C12A-4 S 240 Table 5. FPGA Package Options Voltage Symbol ...

Page 6

... OR2C/T15B, while the OR2C/T26A and the OR2C/2T40A/B use the SQFP2. The OR2TxxA and OR2TxxB series is not offered in the 304-pin SQFP/SQFP2 packages. The OR2C40A is not offered in a 352-pin PBGA. www.latticesemi.com Copyright © 2005 Lattice Semiconductor All Rights Reserved December 2005 PN99-072FPGA_A 208-Pin ...

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