SST25VF032B-50-4C-S2AF Microchip Technology, SST25VF032B-50-4C-S2AF Datasheet - Page 19

• Manufacturer Part Number: SST25VF032B-50-4C-S2AF
• Description: Flash 32Mbit 50MHz
• Manufacturer: Microchip Technology

Specifications of SST25VF032B-50-4C-S2AF

• Product Category: Flash
• Rohs: yes
• Data Bus Width: 1 bit
• Memory Type: Flash
• Memory Size: 32 Mbit
• Architecture: Sectored
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 15 mA
• Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Organization: 4 KB x 1024

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©2011 Silicon Storage Technology, Inc.
Enable-Write-Status-Register (EWSR)
Write-Status-Register (WRSR)
The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR)
instruction and opens the status register for alteration. The Write-Status-Register instruction must be
executed immediately after the execution of the Enable-Write-Status-Register instruction. This two-
step instruction sequence of the EWSR instruction followed by the WRSR instruction works like soft-
ware data protection (SDP) command structure which prevents any accidental alteration of the status
register values. CE# must be driven low before the EWSR instruction is entered and must be driven
high before the EWSR instruction is executed.
The Write-Status-Register instruction writes new values to the BP3, BP2, BP1, BP0, and BPL bits of
the status register. CE# must be driven low before the command sequence of the WRSR instruction is
entered and driven high before the WRSR instruction is executed. See Figure 19 for EWSR or WREN
and WRSR instruction sequences.
Executing the Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to
‘1’. When the WP# is low, the BPL bit can only be set from ‘0’ to ‘1’ to lock-down the status register, but
cannot be reset from ‘1’ to ‘0’. When WP# is high, the lock-down function of the BPL bit is disabled and
the BPL, BP0, and BP1 and BP2 bits in the status register can all be changed. As long as BPL bit is
set to ‘0’ or WP# pin is driven high (V
the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In this
case, a single WRSR instruction can set the BPL bit to ‘1’ to lock down the status register as well as
altering the BP0, BP1, and BP2 bits at the same time. See Table 2 for a summary description of WP#
and BPL functions.
Figure 19:Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and Write-Sta-
SCK
CE#
SO
SI
MODE 3
MODE 0
tus-Register (WRSR) Sequence
0 1 2 3 4 5 6 7
MSB
50 or 06
IH
) prior to the low-to-high transition of the CE# pin at the end of
19
HIGH IMPEDANCE
MODE 3
MODE 0
MSB
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
32 Mbit SPI Serial Flash
01
MSB
7 6 5 4 3 2 1 0
REGISTER IN
STATUS
SST25VF032B
S71327-04-000
Data Sheet
1327 F20.0
02/11