FT220XS-R FTDI, FT220XS-R Datasheet - Page 16

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FT220XS-R

Manufacturer Part Number
FT220XS-R
Description
USB Interface IC USB to 4 bit SPI / FT1248 IC SSOP-16
Manufacturer
FTDI
Datasheet

Specifications of FT220XS-R

Rohs
yes
Product
USB 2.0
Data Rate
12 Mbps, 480 Mbps
Interface Type
USB
Operating Supply Voltage
2.97 V to 5.5 V
Operating Supply Current
9.7 mA to 12.3 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SSOP-16
Tradename
X-Chip

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
FT220XS-R
Manufacturer:
FTDI
Quantity:
3 706
address eeprom
write eeprom
read eeprom
read usb status
Reserved
Table 5.1: FT1248 Commands
5.3 LSB or MSB Selection
The data can be sent/received Least Significant Bit First (LSB) or Most Significant Bit First (MSB). To
determine which mode is used by the FT1248 interface of the FT220X the MTP memory must be set.
This may be selected with FT_PROG.
5.4 Clock Phase/Polarity
The FT1248 slave does not need to have any knowledge of clock rate as this is supplied by the FT1248
master. However the relationship between clock and data needs to be controllable, to allow the slave to
operate in the same way as the master such that data is correctly driven and sampled on the correct
clock phases. By configuring the polarity and phase of CLK with respect to the data it is possible to match
the FT1248 master.
There are 4 possible modes which are determined by the Clock Polarity (CPOL) and Clock Phase (CPHA)
signals. The different combinations of these signals are commonly referred to as modes, see Table 5.2
below. For the FT1248 slave, only 2 of these 4 modes are supported. CPHA will always be set to 1 in the
FT1248 slave because data is available or driven on to MIOSIO wires on the first clock edge after CS# is
active and is therefore sampled on the trailing edge of the first clock pulse. When CPHA equals 0, it
means data must be available or driven onto the MIOSIO wires on the first leading edge of the clock after
CS# is active. However, during this period between CS# becoming active and the first leading clock edge
is when the MIOSIO wires are being “turned around” as when CS# is inactive the FT1248 slave is driving
the write buffer status. Supporting CPHA = 0 would result in bus contention and therefore, shall not be
supported.
Table 5.2: CPOL & CPHA Mode Numbers
Copyright © 2013 Future Technology Devices International Limited
0x05
0x06
0x07
0x08
0x09 – 0xF
Mode
0
1
2
3
FT220X USB 4-BIT SPI/FT1248 IC Datasheet
CPOL
0
0
1
1
buffer
Address EEPROM command sets the address users wish to
write or read from
Write EEPROM command sets the write data to be written into
the EEPROM
Read EEPROM command reads
Read USB Status:
00 = suspended, 01 = default, 10 = addressed, 11 =
configured
Unused Commands
CPHA
0
1
0
1
Document No.: FT_000629 Clearance No.: FTDI# 262
Supported
NO
YES
NO
YES
Version 1.2
16

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