MAX9210EUM-D Maxim Integrated, MAX9210EUM-D Datasheet - Page 10

• Manufacturer Part Number: MAX9210EUM-D
• Description: Serializers & Deserializers - Serdes 21-Bit DC-Balanced Deserializer
• Manufacturer: Maxim Integrated
• Type: Deserializerr

Specifications of MAX9210EUM-D

• Data Rate: 600 Mbit/s
• Input Type: LVDS
• Output Type: LVCMOS/LVTTL
• Number Of Inputs: 3
• Number Of Outputs: 21
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TSSOP-48 EP
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

the voltage rating of the capacitor. The typical LVDS dri-
ver output is 350mV centered on an offset voltage of
1.25V, making single-ended output voltages of 1.425V
and 1.075V. An LVDS receiver accepts signals from 0 to
2.4V, allowing approximately ±1V common-mode differ-
ence between the driver and receiver on a DC-coupled
link (2.4V - 1.425V = 0.975V and 1.075V - 0V = 1.075V).
Common-mode voltage differences may be due to
ground potential variation or common-mode noise. If
there is more than ±1V of difference, the receiver is not
guaranteed to read the input signal correctly and may
cause bit errors. AC-coupling filters low-frequency
ground shifts and common-mode noise and passes
high-frequency data. A common-mode voltage differ-
ence up to the voltage rating of the coupling capacitor
(minus half the differential swing) is tolerated. DC-bal-
anced coding of the data is required to maintain the dif-
ferential signal amplitude and limit jitter on an
AC-coupled link. A capacitor in series with each output
Programmable DC-Balance
21-Bit Deserializers
Figure 11. DC-Coupled Link, Non-DC-Balanced Mode
10
______________________________________________________________________________________
PWRDWN
TxCLK IN
TxIN
7
7
7
7 : 1
7 : 1
7 : 1
PLL
21:3 SERIALIZER
MAX9209
MAX9213
TxOUT
TxCLK OUT
TRANSMISSION LINE
of the LVDS driver is sufficient for AC-coupling.
However, two capacitors—one at the serializer output
and one at the deserializer input—provide protection in
case either end of the cable is shorted to a high voltage.
Voltage droop and the DSV of transmitted symbols
cause signal transitions to start from different voltage
levels. Because the transition time is finite, starting the
signal transition from different voltage levels causes
timing jitter. The time constant for an AC-coupled link
needs to be chosen to reduce droop and jitter to an
acceptable level.
The RC network for an AC-coupled link consists of the
LVDS receiver termination resistor (R
output resistor (R
itors (C). The RC time constant for two equal-value
100Ω
100Ω
100Ω
100Ω
RxCLK IN
RxIN
Selection of AC-Coupling Capacitors
Applications Information
3:21 DESERIALIZER
O
MAX9210
MAX9214
MAX9220
MAX9222
), and the series AC-coupling capac-
1 : 7
1 : 7
1 : 7
PLL
7
7
7
T
), the LVDS driver
RxOUT
PWRDWN
RxCLK OUT