C8051F544-IQR Silicon Labs, C8051F544-IQR Datasheet - Page 88

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C8051F544-IQR

Manufacturer Part Number
C8051F544-IQR
Description
8-bit Microcontrollers - MCU 50 MIPS 8 kB 1kB LIN 2.1 SPI UART I2C
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F544-IQR

Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit

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C8051F54x
the DPTR can be accessed through the SFR registers DPH, which contains the upper 8-bits of DPTR, and
DPL, which contains the lower 8-bits of DPTR.
11.3.2. 8-Bit MOVX Example
The 8-bit form of the MOVX instruction uses the contents of the EMI0CN SFR to determine the upper 8-bits
of the effective address to be accessed and the contents of R0 or R1 to determine the lower 8-bits of the
effective address to be accessed. The following series of instructions read the contents of the byte at
address 0x1234 into the accumulator A.
SFR Definition 11.1. EMI0CN: External Memory Interface Control
SFR Address = 0xAA; SFR Page = 0x00
88
Name
Reset
7:0 PGSEL[7:0] XRAM Page Select Bits.
Bit
Type
Bit
MOV
MOV
MOVX
Name
7
0
EMI0CN, #12h
R0, #34h
a, @R0
The XRAM Page Select Bits provide the high byte of the 16-bit external data memory
address when using an 8-bit MOVX command, effectively selecting a 256-byte page of
RAM.
0x00: 0x0000 to 0x00FF
0x01: 0x0100 to 0x01FF
...
0xFE: 0xFE00 to 0xFEFF
0xFF: 0xFF00 to 0xFFFF
6
0
5
0
; load high byte of address into EMI0CN
; load low byte of address into R0 (or R1)
; load contents of 0x1234 into accumulator A
Rev. 1.1
4
0
PGSEL[7:0]
R/W
Function
3
0
2
0
1
0
0
0

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