PCA9509PGM,125 NXP Semiconductors, PCA9509PGM,125 Datasheet
PCA9509PGM,125
Specifications of PCA9509PGM,125
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PCA9509PGM,125 Summary of contents
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PCA9509P Low power level translating I Rev. 1 — 14 August 2012 1. General description The PCA9509P is a level translating I that enables processor low voltage 2-wire serial bus to interface with standard I SMBus I/O. While retaining all ...
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... NXP Semiconductors 1.1 Selection recommendations The PCA9509P should be used if an external A-port pull-up resistor is required to adjust current for noise margin considerations or to reduce operating current consumption. See Table 1 Table 1. Concern A-port — lowest voltage A-port — current source operating current standby current EN = LOW ...
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... NXP Semiconductors 3. Ordering information Table 2. Type number PCA9509PDP PCA950PGM [1] ‘X’ will change based on date code. 4. Functional diagram Fig 1. PCA9509P Product data sheet Low power level translating I Ordering information Topside Package mark Name Description 9509P TSSOP8 plastic thin shrink small outline package; ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning V Fig 2. 5.2 Pin description Table 3. Symbol V CC(A) [1] A1 [1] A2 GND EN [ CC(B) [1] Port A and port B can be used for either SCL or SDA. PCA9509P Product data sheet Low power level translating CC(A) CC( PCA9509PDP GND ...
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... NXP Semiconductors 6. Functional description Refer to The PCA9509P enables I without degradation of system performance. The PCA9509P contains 2 bidirectional open-drain buffers specifically designed to support up-translation/down-translation between the low voltage and 3.3 V SMBus over-voltage tolerant to 5.5 V even when the device is unpowered. The PCA9509P includes a power-up circuit that keeps the output drivers turned off until V is above 1 ...
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... NXP Semiconductors The enable pin should only change state when the bus and the repeater port are in an idle state to prevent system failures. Because the enable pin (EN) can put the PCA9509P in Standby mode, and when in standby the current mirrors are turned OFF to save power, the recovery from the disabled/standby state is slow so that the current mirrors can return to full current before the channels are enabled ...
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... NXP Semiconductors is high the current should be set near the maximum current drive for the weakest part. However, if the bus capacitance is low a lower current/higher resistor value should be used to keep the rise time from getting so fast that it causes problems. The A side pull-up resistor must be selected keep the LOW-level voltage at the A side input below ...
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... NXP Semiconductors 7. Application design-in information A typical application is shown C-bus while the slave is connected to a 3.3 V bus. Both buses run at 400 kHz. Master devices can be placed on either bus. Fig 4. When port B of the PCA9509P is pulled LOW by a driver on the I hysteresis input detects the falling edge when it goes below 0.3V internal driver on port A to turn on, causing port A to pull down to about 0 ...
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... NXP Semiconductors SCL SDA Fig 6. 8. Limiting values Table 4. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol V CC(B) V CC(A) V I tot T stg T amb [1] With I/O pins OFF. If active, see I PCA9509P Product data sheet Low power level translating I ...
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... NXP Semiconductors 9. Static characteristics Table 5. Static characteristics GND = +85 amb Symbol Parameter Supplies V supply voltage port B CC(B) V supply voltage port A CC(A) I supply current port A CC(A) I supply current port B CC(B) I standby port B supply current CC(B)stb Input and output of port A (A1 to A2) ...
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... NXP Semiconductors [2] Care must be taken to minimize the resistance in series with the ground pin of the PCA9509P to the ground reference point of the V supply because there is only 80 mV margin between the power good threshold and the 0.8 V minimum supply voltage at cold temperature (40 C). Because the B-side I ...
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... NXP Semiconductors 10.1 AC waveforms input 0.5V CC(B) t PHL 70 % 0.5V output 0.5V CC( Fig 7. Propagation delay times and slew rate; port B to port A Fig 9. Propagation delay from the port A’s external driver switching off to port B LOW-to-HIGH transition; port A to port B 10.2 Performance curves 180 time (ns) (1) 160 ...
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... NXP Semiconductors 0.06 (1) SR (V/ns) 0.04 (2) 0.02 (3) (4) 0 −50 − 1 3.3 V CC(A) CC(B) (1) Slew rate of falling signal, port B (2) Slew rate of rising signal, port B (3) Slew rate of falling signal, port A (4) Slew rate of rising signal, port A Fig 12. Typical slew rate versus ambient temperature − ...
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... NXP Semiconductors 170 time (1) (ns) 150 130 (2) 110 (3) 90 (4) 70 2.0 2.5 3.0 3.5 4 1.1 V amb CC(A) (1) Port A t PHL (2) Port A t PLH (3) Port B t PLH2 (4) Port B t PHL Fig 16. Typical propagation delay versus port B supply voltage = 27 1.1 V amb CC(A) (1) Slew rate of falling signal, port B ...
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... NXP Semiconductors 11. Test information Fig 19. Test circuit for open-drain outputs Fig 20. Test circuit for open-drain outputs PCA9509P Product data sheet Low power level translating I PULSE OPEN-DRAIN GENERATOR BUFFER load resistor; 1.35 k load capacitance includes jig and probe capacitance ...
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... NXP Semiconductors 12. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors XQFN8: plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1 terminal 1 index area terminal 1 index area L 1 Dimensions (1) Unit max 0.5 0.05 0.25 1.65 mm nom 0.20 1.60 min 0.00 0.15 1.55 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline ...
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... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 23. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 9. Acronym CDM CMOS CPU ESD HBM I/O 2 C-bus I NMOS RC SMBus 15. Revision history Table 10. Revision history ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Selection recommendations . . . . . . . . . . . . . . . 2 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 6.1 Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 6.2 I C-bus systems . . . . . . . . . . . . . . . . . . . . . . . . 6 6.3 Edge rate control . . . . . . . . . . . . . . . . . . . . . . . 6 6.4 Bus pull-up resistor selection . . . . . . . . . . . . . . 6 6.4.1 Port A pull-up resistor sizing . . . . . . . . . . . . . . . 7 6 ...